22 FN7911.2 April 25, 2013 allowing the receiver to auto-detect the lane configuration if desired. After completion of the ILA the JES" />
參數(shù)資料
型號(hào)： ISLA224S20IR1Z
廠商： Intersil
文件頁(yè)數(shù)： 15/38頁(yè)
文件大?。?/td> 0K
描述： IC ADC
標(biāo)準(zhǔn)包裝： 1
系列： *
ISLA224S
22
FN7911.2
April 25, 2013
allowing the receiver to auto-detect the lane configuration if
desired.
After completion of the ILA the JESD204 transmitter begins
transmitting ADC sample data. Continuous link and lane
alignment monitoring is accomplished via an octet substitution
scheme. The last octet in each frame, if identical to the last octet
in the previous frame, is replaced with a specific control
character. If both sides of the link support lane synchronization,
the last octet in each multi-frame, if identical to the last octet in
the previous frame, is replaced with a different specific control
character. A more complete description of the link initialization
sequence, including finite state machine implementation, can be
found in the JESD204 rev A standard.
LANE DATA RATE
The lane data rate for this product family is a function of the ADC
sample rate, the number of SERDES lanes used, and packing
mode selected in the SERDES transmitter. Figure 51 illustrates
the relationship between ADC sample rate and SERDES lane rate
for various transmitter configurations. The SERDES can typically
operate from lane rates of 1 to over 4.375Gbs. For each ADC
speed grade, the SERDES lanes are tested at its maximum ADC
sample rate using three lane efficient packing as well as two-
lane, efficient packing for the 125MSPS speed version.
LANE DATA RATE CHART
SCRAMBLER
The bypassable scrambler is compliant with the scrambler
defined in the JESD204 rev A standard.
This implementation seeds the scrambler with the initial lane
alignment sequence, such that the first two octets following the
sequence can be properly descrambled if the receiver also
passes the lane alignment sequence through its descrambler.
Even if the receiver does not implement this detail, the 3rd and
subsequent octets can be descrambled to yield ADC data due to
the self-synchronizing nature of the scrambler used.
MULTI-CHIP TIME ALIGNMENT
The JESD204 standard (in various revisions) provides the
capability to time align multiple JESD204 ADC devices to a single
logic device (FPGA or ASIC). This feature is critical in many
applications that cannot tolerate the variable latency of the
JESD204 link, and that must process pipeline depth correct data
from more than one ADC device.
Time alignment of multiple devices provides the capability to
align samples from multiple JESD204 ADC devices in the system
in a pipeline-depth correct manner, thus enabling the system to
analyze the ADC data from multiple devices while eliminating the
variable latency of the JESD204 link as a concern. This capability
enables configurations of JESD204 ADCs as IQ, interleave,
and/or simultaneously-sampled converters.
This ADC family uses the asserted to de-asserted SYNC~
transition as the absolute time event with which to generate a
known sequence of characters at the JESD204 transmitter of
equal pipeline depth between all ADC devices in the system to be
time aligned. This is consistent with the JESD204 rev B
subclass 2 device definition.
Test Patterns
The complexity of the JESD204 interface merits much more test
pattern capability than less complex parallel interfaces. This
device family consequently supports a much wider range of test
patterns than previous ADC families.
Supported test patterns include both transport and link layer
patterns. Transport layer patterns are passed through the
transport layer of the JESD204 transmitter, following the same
sequence of being packed and sliced into octets as the ADC
sample data. Link layer test patterns bypass the transport layer
and are injected directly into the 8b/10b encoder, serialized, and
sent out of the physical media. Test pattern generation is
controlled through SPI register 0xC0.
Link layer PRBS patterns are standard PRBS patterns that can be
used with built-in standard PRBS checkers in, for example, FPGA
SERDES-capable pins.
All transport layer test patterns re-initialize their phase when the
SYNC~ de-assertion occurs; consequently, a system that provides
a well-timed SYNC~ signal with respect to the ADC sample clock
can expect transport layer test patterns to have consistent phase
with respect to that de-assertion, which can be a significant aid
when debugging the system.
1000
1500
2000
2500
3000
3500
4000
4500
50
70
90
110
130
150
170
190
210
230
250
ADC SAMPLE RATE (MSPS)
FIGURE 51. LANE DATA RATE AS A FUNCTION OF PACKING AND
ADC SAMPLE RATE
L
ANE
RATE
(MBPS)
4.375 GBPS
3.125 GBPS (JESD204)
2 Lanes (Simple Packing)
2 Lanes (Efficient Packing)
3 Lanes (Efficient Packing)
3 Lanes (Simple Packing)
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