參數(shù)資料
型號： ISLA212P20IRZ
廠商： Intersil
文件頁數(shù)： 1/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 468mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： *
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
12-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA212P
The ISLA212P is a series of low power, high performance
12-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge technology on a standard CMOS
process, the series supports sampling rates of up to 250MSPS.
The ISLA212P is part of a pin-compatible family of 12 to 16-bit
A/Ds with maximum sample rates ranging from 130MSPS to
500MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset. Digital output data is presented in
selectable LVDS or CMOS formats, and can be configured as
full-width, single data rate (SDR) or half-width, double data
rate (DDR). The ISLA212P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
Key Specifications
SNR @ 250/200/130MSPS
70.5/71.0/71.5dBFS fIN = 30MHz
68.7/68.9/68.8dBFS fIN = 363MHz
SFDR @ 250/200/130MSPS
83/83/88dBc fIN = 30MHz
78/81/85dBc fIN = 363MHz
Total Power Consumption = 440mW @ 250MSPS
Features
Single Supply 1.8V Operation
Clock Duty Cycle Stabilizer
75fs Clock Jitter
700MHz Bandwidth
Programmable Built-in Test Patterns
Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
Nap and Sleep Modes
- 200s Sleep Wake-up Time
Data Output Clock
SDR/DDR LVDS-Compatible or LVCMOS Outputs
Selectable Clock Divider
Applications
Radar Array Processing
Software Defined Radios
Broadband Communications
High-Performance Data Acquisition
Communications Test Equipment
DIGITAL
ERROR
CORRECTION
VINP
VINN
CLOCK
MANAGEMENT
SHA
12-BIT
250 MSPS
ADC
CLKP
CLKN
SPI
CONTROL
CSB
SC
LK
SD
IO
O
VSS
A
VSS
AV
D
CLKOUTP
CLKOUTN
D[11:0]N
OV
DD
CL
K
D
IV
RLV
D
S
SD
O
+
–
VCM
R
ESE
T
N
CL
KD
IV
R
S
T
P
CL
KD
IV
R
S
T
N
NA
P
S
L
P
D[11:0]P
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA216P25
16
250
ISLA216P20
16
200
ISLA216P13
16
130
ISLA214P50
14
500
ISLA214P25
14
250
ISLA214P20
14
200
ISLA214P13
14
130
ISLA212P50
12
500
ISLA212P25
12
250
ISLA212P20
12
200
ISLA212P13
12
130
November 30, 2012
FN7717.2
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