參數(shù)資料
型號(hào): ISL97653A
廠商: Intersil Corporation
英文描述: 5-Channel Integrated LCD Supply
中文描述: 5通道集成LCD電源
文件頁數(shù): 16/18頁
文件大小: 523K
代理商: ISL97653A
16
FN6367.0
December 6, 2007
V
ON
Slice Circuit
The V
ON
slice circuit functions as a three way multiplexer,
switching the voltage on COM between ground, DRN and
POUT, under control of the start-up sequence and the CTL pin.
During the start-up sequence, COM is pulled to ground via
an NDMOS FET with R
DS(on)
of 260 ohms. After the start-up
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 30
Ω
internal MOSFET, and if CTL is high,
COM connects to P
OUT
internally via a 5
Ω
MOSFET.
The slew rate of the switch control circuit is mainly restricted
by the load capacitance at COM pin and is given by
Equation 20:
V
i
Where V
g
is the supply voltage applied to DRN or voltage at
P
OUT
, which range is from 0V to 30V. R
i
is the resistance
between COM and DRN or P
OUT
including the internal
MOSFET r
DS(on)
, the trace resistance and the resistor
inserted, R
L
is the load resistance of VON slice circuit, and
C
L
is the load capacitance of switch control circuit.
In the Typical Application Circuit, R
8
, R
9
and C
22
give the
bias to DRN based on Equation 21:
And R
10
can be adjusted to adjust the slew rate.
V
LOGIC2
LDO
An LDO controller is also integrated to provide a second
logic supply. The LDO-CTL pin drives the base of an
external transistor which should be sized for the current
required. A resistor divider is used to set the output voltage
by feeding back a reference voltage to LDO-FB. The internal
feedback reference is 1.215V.
HVS Operation
When the HVS input is taken high, the ISL97653A enters
HVS test mode. In this mode, the output of A
VDD
is
increased by switching RSET to ground, and the AVDD is
set to:
Where R
x
is the value of R
4
in parallel with R
5
. AVDD
voltage higher than the maximum rating of the boost
MOSFET may damage the part.
Fault Protection
The ISL97653A incorporates a number of fault protection
schemes. AVDD, VON, and VOFF are constantly monitored.
If fault conditions are detected for longer than 1ms on these
FB inputs, the device stops switching and the outputs are
disconnected. The ISL97653A also integrates over temp and
over current protection.
Supply Sequencing
When the input voltage V
IN
is higher than 4V(UVLO), V
REF
,
V
LOGIC,
and V
LOGIC2
are turned on. V
LOGIC
has a 9ms
fixed soft-start at start-up. A
VDD
, V
ON
, and V
OFF
are
dependant on the EN pin.
FIGURE 17. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
FAULT
0.2V
CLK
EN
VDD
SUPN
FBN
NOUT
PGND
STOP
PWM
CONTROL
V
REF
R6
40k
C20
820pF
C19
100pF
R7
328k
V
OFF
(-8V)
C13
470nF
D2
D3
C12
220nF
A2
0.4V
A1
M1
M2
1.2MHz
V
Δ
t
-------
L
L
------------------------------------
=
(EQ. 20)
V
DRN
V
R
+AVDD R
8
9
+
8
---------------------------------------------------------
=
(EQ. 21)
A
VDD
R
--------------------
R
x
+
x
V
FBB
×
=
(EQ. 22)
ISL97653A
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