參數(shù)資料
型號(hào)： ISL97652IRZ-TK
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： 4-Channel Integrated LCD Supply with Dual VCOM Amplifiers
中文描述： 2.5 A SWITCHING REGULATOR, 1500 kHz SWITCHING FREQ-MAX, PQCC48
封裝： 7 X 7 MM, ROHS COMPLIANT, PLASTIC, MO-220VKKD-2, QFN-48
文件頁(yè)數(shù)： 23/25頁(yè)
文件大?。?/td> 709K
代理商： ISL97652IRZ-TK
23
FN9287.0
December 21, 2006
outputs are in regulation by the time this threshold is
reached. For example, SSB controls step-down regulator
fault checking, DEL1 controls V
OFF
fault checking, SS
controls step-up regulator and PFET fault checking, DEL2
controls V
ON
and GPM fault checking. If a fault on any of the
major blocks is detected continuously for a predetermined
time interval (currently set to 63μs), when fault checking is
enabled for that function, the fault latch will be set. This
causes all major functions to be disabled immediately,
including the 5.3V regulator. Once VDC falls below its
internal UVLO limit (typically 3.6V), the FAULT latch is reset.
This will initiate an automatic restart. If the fault has been
cleared, the restart will be successful; if the fault persists, the
FAULT latch will again be set, and the cycle will repeat itself.
Buck, boost and V
ON
circuits have fault thresholds at 90% of
target values.
The V
OFF
fault threshold is set at 125mV above the 0.5V
regulation point.
GPM fault detection is designed to detect a short circuit on
the output, by monitoring whether VGHM fails to pull up to
VGH on two consecutive F
OSC
clock periods.
The A
VDD
PFET also has fault checking, which will protect
the FET in the event of an output short circuit.
Note that the V
COM
amplifiers are independently biased,
and are enabled at all times, except if an over-temperature
fault is detected. If this behavior is not desired, then there is
an option to power the V
COM
amplifiers from A
VDD
, which
will keep them disabled until the boost is enabled.
Note also that it is possible to prevent timed fault checking
on any or all of the major functions, simply by externally
clamping SSB, SS, DEL1 and/or DEL2 to a voltage between
1.3V and 2V.
PCB Layout Procedure
To ensure the user gets the best chip performance with
minimum amount of PCB rework in the development phase,
the following PCB layout procedure is strongly
recommended.
PCB metal layers
Reserve the top PCB metal layer for direct power ground
(PGND) connections to the supply pins and switching
outputs (buck/boost/charge-pumps). The goal is to ensure
there are no VIAS in the boost and buck paths to the
smoothing capacitors. The top layer may also be used for
general routing of non-sensitive tracks as long as this does
not compromise the supply track widths which should be as
wide as possible.
Note that using VIAs in series with smoothing capacitors
(even if implemented as multiply parallel VIAs) increases the
effective high frequency ESR of the capacitors and WILL
cause degraded system operation.
(Route the following tracks on the PGND (top) metal layer:
PGND1,2,3 [a single wide track] to CIN, Cout and CB, D5.
SW1,2 [a single wide track] to L1/D1, SWB1,2 [a single wide
track] to L2/D5.)
Reserve the bottom (or an intermediate layer) for the signal
ground plane (SGND) and signal routing. It is recommended
that all feedback inputs and any other sensitive tracks are
routed to the SGND layer using a VIAs as close to the chip
as possible. This prevents unwanted interference pick-up
and allows the supply smoothing capacitors to be places as
close to the chip as possible.
(Route the following tracks on the SGND (bottom or
intermediate) metal layer: FB, FBB, FBP, FBN, POS1,2, )
Star Ground
A star ground system is where a number of different grounds
(e.g. PGND, SGND°|) come together at a single location
which then becomes the reference ground point for the
system as a whole. Star grounding ensures minimum
interference between different functions in a system.
Practically, it is difficult to achieve an ideal (single location)
ground point due to the physical dimensions of the chip,
smoothing capacitors and track routing, however, the
exposed die plate and the area immediately next to the
PGND1,2,3 pins is defined as the star ground for this chip.
The negative smoothing capacitor terminals of: Cout, CB
and CIN must be located as close as possible to the
PGND1,2,3 pins. The smoothing capacitors for VIN, Cout
and CB come as a block of three or four capacitors with
(usually) one small capacitor whose role is to reduce the
total effective ESR of the capacitors. It is recommended that
the small capacitor and at least one of the large capacitors
from each capacitor block is placed as physically close to the
chip PGND pins as possible. The other capacitors from each
block can be placed a little further away, if necessary.
Exposed Die plate connection
The exposed die plate connection to the underside of the
chip must directly connect the PGNDs (pins 34,35,36) and
AGND (pin 15) with an equivalent area of metal. The other
ground pins (amplifier OGND and charge pump GND pins
may also be connected to the die plate.
The exposed die plate connection must have multiple VIAs
(use a 4x4 array) connecting the top metal PGND layer to
the bottom SGND metal layer. The bottom SGND metal area
around the VIA array should be maximized in order to keep
the thermal resistance of the chip and PCB system as low as
possible. This will optimise operation at high currents or in
high ambient temperature applications.
Order of component placement
The order of component placement should be as follows.
This procedure minimizes the high current PGND and supply
track impedance to the chip pins.
ISL97652
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