參數(shù)資料
型號: ISL97652IRZ-TK
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: 4-Channel Integrated LCD Supply with Dual VCOM Amplifiers
中文描述: 2.5 A SWITCHING REGULATOR, 1500 kHz SWITCHING FREQ-MAX, PQCC48
封裝: 7 X 7 MM, ROHS COMPLIANT, PLASTIC, MO-220VKKD-2, QFN-48
文件頁數(shù): 19/25頁
文件大?。?/td> 709K
代理商: ISL97652IRZ-TK
19
FN9287.0
December 21, 2006
High Performance V
COM
Amplifiers
The integrated high performance amplifiers are designed to
drive the V
COM
plane in TFT-LCD displays. Under normal
operational conditions, the amplifiers are permanently
enabled when the AVIN supply is present. Under fault
conditions and with EN1 active, the temperature shut-down
(T
OFF
exceeded) will disable the amplifiers until the
temperature drops to T
ON
. Temperature shut-down of the
amplifiers is disabled if EN1 is disabled.
The amplifiers integrated in to the ISL97652 feature high
output current of 50mA minimum and high slew rate of
50V/μs. Both inputs and outputs have rail-to-rail capability.
Start-Up Sequence Control
The ISL97652 features extensive start-up sequence control
options. Two enable pins and two delay control pins are
used to set the start-up sequence.
The EN1 enable pin controls the buck regulator and negative
charge pump controller. When EN1 goes H, the internal 5.3V
regulator starts up. Once the regulator output on pin 27
(VDC) exceeds it's UVLO threshold, the REF pin starts to
charge up to the normal output level. Once REF is within
15% of it's final value, the buck regulator will start to operate.
Note that if V
REF
moves more than 15% from it's target
value, all major functions will be disabled until REF returns to
it's normal range. This involves the chip going through the
normal start-up sequence from buck start-up onwards,
depending on the state of the enable signals EN1, EN2. The
soft-start time is set using the capacitor connected to SSB.
Once the output reaches 90% the DLY1 capacitor begins to
charge. Once the threshold is reached, the negative charge
pump will begin. Removing the DLY1 capacitor will cause the
negative charge pump to start immediately once the buck
regulator reaches 90% of the target value. The delay time
and soft-start times are determined using the following
equations:
V
DL1
The EN2 pin is used to control the boost and positive charge
pump circuits.Note that EN2 is ignored until the buck
converter has reached 90% of it's target value. When taken
high, the internal PFET is turned on to connect the input to
the A
VDD
output. A capacitor connected to SUI provides
control over the soft connect to limit inrush current. Next, the
boost converter starts to operate. The soft-start time for the
boost is set using the capacitor tied to the SS pin. Once the
output reaches 90% of the target value, the DLY2 timer
starts. Once completed, the positive V
ON
charge pump
starts to operate. If CDL2 is not present, the V
ON
charge
pump will start immediately once the boost is in regulation.
The delay time is determined using the following equation:
~1.94V
0
0
0
t
t
t
VGHM
VFLK
CE
~1.265V
T
CE
FIGURE 21. VON-SLICE TIMING WAVEFORM
SLOPE CONTROLLED
BY RE AND LOAD
CAPACITANCE
VGL
VGH
DELAY TIME CONTROLLED BY CE
T
DLY1
C
DL1
--------------
×
=
(EQ. 20)
T
SSB
C
SSB
V
SSB
--------------
×
=
(EQ. 21)
T
DLY2
C
DL2
V
DL2
--------------
×
=
(EQ. 22)
T
SS
C
SS
V
SS
-----------
×
=
(EQ. 23)
ISL97652
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