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參數(shù)資料
| 型號(hào)： | ISL9206EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | FlexiHash For Battery Authentication |
| 中文描述： | FlexiHash對(duì)于電池認(rèn)證 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 364K |
| 代理商： | ISL9206EVAL1 |
11
FN9260.0
March 9, 2006
Bus Transaction Protocol
The XSD bus for the ISL9206 defines three types of bus
transactions. Figure 10 shows the bus transaction protocol.
The blue color represents the signal sent by the host and the
green color stands for the signal sent by the device. Before
the transaction starts, the host should make sure that the
XSD device is not in the sleep mode. One method is to
always send a ‘break’ signal before starting the transaction,
as shown in Figure 10. If the device is not in the sleep mode,
the ‘break’ signal is not mandatory. The ‘break’ pulse width
may appear to be wider than what the host sends out
because of the reason explained in Figure 4. The symbols in
Figure 10 are explained in Table 7.
Passive CRC Support
The CRC feature only supports the read transaction in the
ISL9206. When the OPCODE in the instruction is ‘10’, an
8-bit CRC is automatically calculated for the data bytes
being transferred out. The CRC result is then appended after
the last data byte is read out.
CRC is generated using the DOW CRC polynomial as
follows:
Polynom = 1 + X
4
+ X
5
+ X
8
The CRC generation algorithm is logically illustrated in
Figure 11. Prior to a new CRC calculation, the LFSR (linear
feedback shift register) is initialized to zero. The read data to
be transmitted out is concurrently shifted into the CRC
calculator. After the actual data is transmitted out, the final
content of the LFSR is the resulting CRC value. This value is
transmitted out after the read data, with LSB being
transmitted out first.
TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL
SYM
DESCRIPTION
MIN
TYP
MAX
IFG
H
Host inter-frame gap
0 BT
H
800ms
IFG
D
Device inter-frame gap
1 BT
D
TA
H
Host turn-around time
1 BT
H
800ms
TA
D
Device turn-around time
1 BT
D
FIGURE 10. XSD BUS TRANSACTION PROTOCOL. THE ‘BREAK’ SIGNAL IS OPTIONAL IF THE DEVICE IS AWAKE
IFGH
H
Write Instruction Frame
Data Frame 1
Data Frame 2
IFG
break
T
SD
TAD
Read Instruction Frame
Data Frame 1
(output from slave)
(output from slave)
Data Frame 2
IFGD
break
T
SD
(output from slave)
D
Read Instruction Frame
Data Frame
Next Instruction
Frame
TA
TAH
break
T
SD
(A) Multi-Byte Write Instruction.
(B) Multi-Byte Read Instruction.
(C) Back-to-Back Transaction (Read Followed by Write).
1st
Stage
2nd
Stage
3rd
Stage
4th
Stage
5th
Stage
7th
Stage
8th
Stage
Data
6th
Stage
LSB
MSB
FIGURE 11. THE CRC CALCULATOR FOR THE PASSIVE CRC SUPPORT
Serial
ISL9206
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL9208 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Multi-Cell Li-ion Battery Pack OCP/Analog Front End |
| ISL9208_0711 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Multi-Cell Li-ion Battery Pack OCP/Analog Front End |
| ISL9208EVAL1Z | 制造商:Intersil Corporation 功能描述:ISL9208 EVALUATION BOARD 1 - ROHS COMPLIANT - QFN - Bulk |
| ISL9208EVAL2Z | 功能描述:EVAL BOARD 2 FOR ISL9208 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| ISL9208IRZ | 功能描述:IC MULTI-CELL LI-ION PROT 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電池管理 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:Impedance Track™ 功能:燃料，電量檢測(cè)計(jì)/監(jiān)控器 電池化學(xué):鋰離子（Li-Ion） 電源電壓:2.4 V ~ 2.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:帶卷 (TR) 產(chǎn)品目錄頁面:1020 (CN2011-ZH PDF) 配用:BQ27350EVM-ND - BQ27350EVM 其它名稱:296-21665-2 |
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