參數(shù)資料
型號(hào)： ISL6742AAZA-T
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： Advanced Double-Ended PWM Controller
中文描述： 0.1 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16
封裝： 0.150 INCH, ROHS COMPLIANT, PLASTIC, SSOP-16
文件頁(yè)數(shù)： 8/18頁(yè)
文件大?。?/td> 422K
代理商： ISL6742AAZA-T
8
FN9183.1
July 25, 2005
Pin Descriptions
VDD -
VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a 0.1
μ
F or larger
high frequency ceramic capacitor as close to the VDD and
GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
GND -
Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a
low impedance layout is necessary. Ground planes and
short traces are highly recommended.
VREF -
The 5.00V reference voltage output having 3%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1
μ
F to 2.2
μ
F low ESR capacitor.
CT -
The oscillator timing capacitor is connected between
this pin and GND. It is charged through an internal 200
μ
A
current source and discharged with a user adjustable current
source controlled by RTD.
RTD -
This is the oscillator timing capacitor discharge
current control pin. The current flowing in a resistor
connected between this pin and GND determines the
magnitude of the current that discharges CT. The CT
discharge current is nominally 20x the resistor current. The
PWM deadtime is determined by the timing capacitor
discharge duration. The voltage at RTD is nominally 2.00V.
The minimum recommended value of RTD is 2.00k
.
CS -
This is the input to the overcurrent comparator and the
average current sample and hold circuit. The overcurrent
comparator threshold is set at 1.00V nominal. The CS pin is
shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a
series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may result in CS being discharged prior to the
power switching device being turned off.
OUTA and OUTB -
These paired outputs are the pulse-
width-modulated outputs for controlling the switching FETs in
alternate sequence.
Typical Performance Curves
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
FIGURE 4. CAPACITANCE vs FREQUENCY
-40
-25
-10
5
20
35
50
65
80
95
110
0.98
0.99
1
1.01
1.02
TEMPERATURE (°C)
N
R
0
200
400
600
800
1000
18
19
20
21
22
23
24
25
RTD CURRENT (μA)
C
0
10
20
30
40
50
60
70
80
90
100
10
100
110
4
RTD (k
)
D
110
3
CT =
1000pF
680pF
470pF
330pF
220pF
100pF
0.1
1
10
10
100
110
3
CT (nF)
F
RTD=
10k
50k
100k
ISL6742
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