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參數(shù)資料
| 型號： | ISL6742AAZA-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Advanced Double-Ended PWM Controller |
| 中文描述： | 0.1 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 422K |
| 代理商： | ISL6742AAZA-T |
11
FN9183.1
July 25, 2005
The average current signal on IOUT remains accurate
provided that the output inductor current is continuous (CCM
operation). Once the inductor current becomes
discontinuous (DCM operation), IOUT represents 1/2 the
peak inductor current rather than the average current. This
occurs because the sample and hold circuitry is active only
during the on time of the switching cycle. It is unable to
detect when the inductor current reaches zero during the off
time.
If average overcurrent limit is desired, IOUT may be used
with the available error amplifier of the ISL6742. Typically
IOUT is divided down and filtered as required to achieve the
desired amplitude. The resulting signal is input to the current
error amplifier (IEA). The IEA is similar to the voltage EA
found in most PWM controllers, except it cannot source
current. Instead, VERR has a separate internal 1mA pull-up
current source.
Configure the IEA as an integrating (Type I) amplifier using
the internal 0.6V reference. The voltage applied at FB is
integrated against the 0.6V reference. The resulting signal,
VERR, is applied to the PWM comparator where it is
compared to the sawtooth voltage on RAMP. If FB is less
than 0.6V, the IEA will be open loop (can’t source current),
VERR will be at a level determined by the voltage loop, and
the duty cycle is unaffected. As the output load increases,
IOUT will increase, and the voltage applied to FB will
increase until it reaches 0.6V. At this point the IEA will
reduce VERR as required to maintain the output current at
the level that corresponds to the 0.6V reference. When the
output current again drops below the average current limit
threshold, the IEA returns to an open loop condition, and the
duty cycle is again controlled by the voltage loop.
The average current control loop behaves much the same
as the voltage control loop found in typical power supplies
except it regulates current rather than voltage.
The EA available on the ISL6742 may also be used as the
voltage EA for the voltage feedback control loop rather than
the current EA as described above. An external op-amp may
be used as either the current or voltage EA providing the
circuit is not allowed to source current into VERR. The
external EA must only sink current, which may be
accomplished by adding a diode in series with its output.
The 4x gain of the sample and hold buffer allows a range of
150 - 1000mV peak on the CS signal, depending on the
resistor divider placed on IOUT. The overall bandwidth of the
average current loop is determined by the integrating current
EA compensation and the divider on IOUT.
The current EA cross-over frequency, assuming R6 >>
(R4||R5), is
where f
CO
is the cross-over frequency. A capacitor in parallel
with R4 may be used to provide a double-pole roll-off.
The average current loop bandwidth is normally set to be
much less than the switching frequency, typically less than
5kHz and often as slow as a few hundred hertz or less. This
is especially useful if the application experiences large
surges. The average current loop can be set to the steady
state overcurrent threshold and have a time response that is
longer than the required transient. The peak current limit can
be set higher than the expected transient so that it does not
interfere with the transient, but still protects for short-term
larger faults. In essence a 2-stage overcurrent response is
possible.
The peak overcurrent behavior is similar to most other PWM
controllers. If the peak current exceeds 1.0V, the active
output pulse is terminated immediately.
If voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
operation. DC blocking capacitors used in voltage-mode
bridge topologies become unbalanced, as does the flux in
the transformer core. The average overcurrent circuitry
prevents this behavior by maintaining symmetric duty cycles
for each half-cycle. If the average current limit circuitry is not
used, a latching overcurrent shutdown method using
external components is recommended.
The CS to output propagation delay is increased by the
leading edge blanking (LEB) interval. The effective delay is
the sum of the two delays and is 130ns maximum.
FIGURE 7. AVERAGE OVERCURRENT IMPLEMENTATION
150 - 1000 mV
+
-
0.6V
S&H
4x
R6
R5
R4
C10
CS
FB
IOUT
1
2
4
3
5
6
7
8
9
10
11
12
13
14
15
16
VERR
ISL6742
f
CO
-----------------------------------
=
Hz
(EQ. 7)
ISL6742
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