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參數(shù)資料
| 型號(hào)： | ISL6740A |
| 廠商： | Intersil Corporation |
| 英文描述： | Flexible Double-Ended Voltage-Mode PWM Controller with Voltage Feed Forward |
| 中文描述： | 靈活的雙端電壓模式PWM控制器與電壓前饋 |
| 文件頁(yè)數(shù)： | 13/15頁(yè) |
| 文件大?。?/td> | 320K |
| 代理商： | ISL6740A |
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13
FN9195.0
February 7, 2005
by 2 corresponds to the duty cycle below which a short
circuit can exist.
where D
SC
is the maximum short circuit duty cycle, V
SCSET
is the voltage applied to SCSET, and D
max
is the maximum
duty cycle. If the timing capacitor voltage fails to exceed the
threshold before an overcurrent pulse is detected, a short
circuit condition exists. A shutdown will occur if 8 short circuit
events occur within 32 oscillator cycles. Once shutdown
occurs, SS will discharge through a 15
μ
A current source. A
new soft-start cycle will begin when SS reaches 0.27V.
Latching shutdown may be implemented in the same
manner as described in the overcurrent section. Short circuit
shutdown is enabled once the soft-start cycle is complete.
Connecting SCSET to GND inhibits short circuit shutdown.
If either R
TC
ar R
TD
are used as the voltage source for the
divider, the effect of the SCSET divider must be included in
the timing calculations since the current sourced from R
TC
and R
TD
determine the charge and discharge currents for
the timing capacitor. Typically the resistor between either
R
TC
or R
TD
and GND is formed by two series resistors with
the center node connected to SCSET.
Alternatively, SCSET may be set using a voltage between
0V and 2V. This voltage divided by 2 determines the
percentage of the maximum duty cycle that corresponds to a
short circuit when current limit is active. For example, if the
maximum duty cycle is 95% and 1V is applied to SCSET,
then the short circuit duty cycle is 50% of 95% or 47.5%.
Fault Conditions
A fault condition occurs if any of the following conditions
occur:
V
REF
falls below 4.65V
UV falls below 1.00V
the internal thermal protection triggers
OTS faults
When any of the above faults are detected, OUTA and
OUTB outputs are disabled, Fault is asserted, and the soft-
start capacitor is quickly discharged. When the fault
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins. Fault is high impedance
during the soft-start cycle unless an active fault is present.
A shutdown resulting from an overcurrent or short circuit
condition also causes assertion of Fault, but the soft-start
capacitor is not quickly discharged. The initiation of a new
soft-start cycle is delayed while the soft-start capacitor is
discharged at a 15
μ
A rate. This reduces the repetition rate of
the hiccup behavior and keeps the average output current to
a minimum.
Thermal Protection
Two methods of over temperature protection are provided.
The first method is an on board temperature sensor that
protects the device should the junction temperature exceed
145
°
C. There is approximately 15
°
C of hysteresis.
The second method uses an internal comparator with a 2.5V
reference (V
REF
/2). The non-inverting input to the
comparator is accessible through the OTS pin. A thermistor
or thermal sensor located at or near the area of interest may
be connected to this input. There is a nominal 25
μ
A switched
current source used to create hysteresis. The current source
is active only during an OT fault; otherwise, it is inactive and
does not affect the node voltage. The magnitude of the
hysteresis is a function of the external resistor divider
impedance. Either a positive temperature coefficient (PTC)
or a negative temperature coefficient (NTC) thermistor may
be used. If a NTC thermistor is desired, position R1 may be
substituted. If a PTC is desired, then position R2 may be
substituted. The threshold with increasing temperature is set
by making the fixed resistance equal in value to the
thermistor resistance at the desired trip temperature.
V
TH
↑
= 2.5V and R1 = R2 (HOT)
To determine the value of the hysteresis resistor, R3, select
the value of thermistor resistance that corresponds to the
desired reset temperature.
5
)
R1
R2
–
R1
R2
+
D
SC
V
2
----------------------
D
max
=
(EQ. 12)
FIGURE 11. OTS HYSTERESIS
V
REF
R1
R2
R3
V
REF
/2
25
μ
A
ON
+
-
V
REF
R3
--------------------------–
=
(EQ. 13)
ISL6740A
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