參數(shù)資料
型號: ISL6595
廠商: Intersil Corporation
英文描述: Digital Multiphase Controller
中文描述: 數(shù)字多相控制器
文件頁數(shù): 9/21頁
文件大?。?/td> 566K
代理商: ISL6595
9
FN9192.0
February 27, 2006
General Description
The ISL6595 is a digital multi-phase pulse width modulation
controller integrated circuit for use in 2- to 6-phase
synchronous buck converter CPU core supply power
switching regulators. The device is optimized for delivering
voltages from 0.5 to 1.6V at high current levels (120A+) with
programmable PWM switching frequencies between 100kHz
and 2MHz. The ISL6595 brings the benefit of digital control
to voltage regulators targeting Intel
VRD/VRM 10.x, 11.0
and similar applications.
The ISL6595 is designed to maximize value to the user by
providing features, monitoring and performance to minimize
the number of required off-chip components, work with a
variety of widely available standard components, and to
accommodate wider device tolerance mismatches than
competing analog controller solutions.
The ISL6595 provides both ease-of-use and flexibility to the
user. Major features include:
Internal Voltage and Temperature Reference – An internal
factory trimmed ±0.5% voltage reference sets the VID
DAC, voltage ADC and current ADC range. In addition, a
proportional-to-absolute-temperature (PTAT) reference is
generated and digitized to serve as the controller
temperature sensor.
Internal Oscillator – Provides a factory trimmed
156.25MHz ±10% clock reference. Fixed and
programmable dividers generate all the needed internal
clocks to configure the controller’s switching frequency
and number of active phases.
Dedicated Voltage ADC – A high precision differential
input voltage ADC digitizes the differential remote sense
voltage. An integrated anti-alias filter and ripple frequency
null filter minimize the impact of high frequency noise on
the system.
Multiplexed Current Sense ADC – The average currents
from each phase are sensed as a voltage across the low
side FET using the multiplexed current ADC. Each phase
is sampled at the middle of its cycle, with timing optimized
through a programmable delay line. The internal
temperature reference and external thermistor
temperature are also digitized using the multiplexed
current ADC. Gain and offset of the sensor and ADC are
compensated through either a one time factory calibration,
or through a power-up calibration each time the output
voltage is reset.
34
ISEN2-
I
Phase channel #2 ADC current sense (-) input, tie to ground if the phase is unused.
35
ISEN2+
I
Analog
Phase channel #2 ADC current sense (+) input.
36
VDD
I
VDD
3.3V power supply connection, decoupling cap should be placed close to pin.
37
PWM2
O
3.3V CMOS
Phase channel #2 PWM output.
38
ISEN1-
I
Phase channel #1 ADC current sense (-) input, tie to ground if the phase is unused.
39
ISEN1+
I
Analog
Phase channel #1 ADC current sense (+) input.
40
PWM1
O
3.3V CMOS
Phase channel #1 PWM output.
41
CAL_CUR_SEN
I
Analog
Calibration current sense input. Measures the voltage across the calibration sense
resistor and adjusts CAL_CUR_EN via an op amp loop such that the voltage across the
resistor is 200mV.
42
CAL_CUR_EN
O
Analog
Calibration current enable output. Drives the calibration FET gate voltage to adjust its
r
DS(on)
such that voltage across the sense resistor is set at 200mV.
43
LL0
I
1.2V CMOS
Processor load line select input control signal (LSB). Selects regulator load line
resistance and loadline offset voltage.
44
RESET_N
I
3.3V CMOS
Active LOW asynchronous system reset to place ISL6595 into default state.
“1”
asynchronous reset disabled
“0”
asynchronous reset enabled
45
SADDR
I
3.3V CMOS
I
2
C address LSB select.
“1”
Address 1110001 selected
“0”
Address 1110000 selected
46
SDA
I
3.3V CMOS
I
2
C interface serial data line.
47
SCL
I
3.3V CMOS
I
2
C interface serial clock line.
48
VD25
I
Analog
Decoupling capacitor for 2.5V internally generated voltage, recommend
0.01
μ
F, 0.1
μ
F max.
Pin Description
(Continued)
PIN #
NAME
I/O
TYPE
DESCRIPTION
ISL6595
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