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參數(shù)資料
| 型號： | ISL6590 |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual Low-Noise Wide-Bandwidth Precision Amplifier 8-PDIP -40 to 85 |
| 中文描述： | 數(shù)字多相位PWM控制器為核心電壓調(diào)節(jié) |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 1525K |
| 代理商： | ISL6590 |
13
Backside Serial Bus (BSB)
The transfer of data on the BSB consists of a start bit, 5 ID
bits, 5 memory address bits, a read/write bit, an address
acknowledge bit, 8 data bits, a data acknowledge bit, and a
stop bit. The rate of transfer is set by the serial clock divider
register.
Background polling of ISL6580 fault registers is performed
using the BSB. The fault information is written to the
ISL6590 local copies of the ISL6580 fault registers. ISL6580
control registers can be written to or read back from the
ISL6590 memory via the BSB.
Startup Process
ISL6580 Enumeration
After power-up of the system, each installed ISL6580 is
polled for its existence. This procedure involves the
Controller to assert the PWM signal for a specific Power IC.
If the specified Power IC is present, it will assert its signal to
acknowledge seeing its PWM asserted. This sequence is
repeated for each Power IC that may be in the system. This
process is known as Device Polling.
After this initial PWM polling is complete, the serial interface
of each Power IC has to be configured with a device ID to be
able to respond to serial commands later. This procedure
involves issuing a “config call” which is to send a serial write
command to global device ID ‘0’. During the data portion of
the cycle, the Power IC to be configured has its PWM signal
asserted by the Controller. This action allows the data bits
that are sent from the Controller to be shifted into a device ID
register within the Power IC. This process is known as
Enumeration.
During enumeration, the address on the serial bus for each
ISL6580 is uniquely defined according to Table 6. If an
address acknowledge bit is not returned, the device is not
used because it is either not present or not functional. The
PWM signals are used to enable address writing to each
ISL6580. Fault processing is disabled during enumeration.
MEMORY
BUS
MUX
MEMORY
(REGISTERS)
STATE
CONTROL/
FAULT
MONITOR
READ
ADDR[15:0]
ADDR[15:0]
DATA[7:0]
DATA[7:0]
WRITE
DONE
OPEN LOOP
WRITE
READ
ASYNCHRONOUS
SERIAL
INTERFACE
(ASI)
FEEDBACK
CONTROL
BACKSIDE
SERIAL
BUS
EEPROM
INTERFACE
STATUS
COEFFICIENTS
CONTROL
STATUS
DONE
WRITE
DEVICE[4:0]
D
A
R
W
DATA[7:0]
ADDR[4:0]
MDI
/MCS
MCLK
MDO
CONTROL
AND
STATUS
REGISTERS
EEPROM
INTERFACE
ISL6580
MAPPED
REGISTERS
ATX
ARX
PWRGD
OUTEN
VID[5:0]
FIGURE 10. MEMORY INTERFACE DIAGRAM
ISL6590
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