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參數(shù)資料
| 型號： | ISL658090EVAL3 |
| 廠商： | Intersil Corporation |
| 英文描述： | Integrated Power Stage |
| 中文描述： | 集成功率級 |
| 文件頁數(shù)： | 26/31頁 |
| 文件大?。?/td> | 1391K |
| 代理商： | ISL658090EVAL3 |
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it. This provides a predicted average current per power
stage (Figure 42). If any individual power stage reaches this
over current protection level, the VRM shuts down and
reports an over current fault condition. This protection
feature can be disabled or enabled via the the user interface
software. The user interface software also allows
programming of the total average output current level where
the fault condition trips.
INPUT AND OUTPUT CAPACITOR SELECTION
The VRM requires capacitors at the input as well as the
output to limit the fluctuation in voltage with a change in
other conditions of the system. These changes include
events such as load variations, VID stepping, start-up and
shutdown.
Input Capacitors
VRM INPUT CAPACITOR:
The VRM is configured as a multi-phase buck converter. By
its nature, a buck converter draws current from the input
source in pulses, as shown in Figure 43 In the absence of an
input capacitor, the high-frequency current pulses would
lead to glitches and ringing at the input voltage with every
current transition. The VRM specification also places an
upper limit on the slew rate of the input current. A capacitor
bank at the input to the VRM provides the pulsed charge to
the VRM and draws an average DC current from the input
supply. As shown in Figure 43, the input capacitor results in
a much lower slew rate of the VRM input current than that of
the high-side current of individual channels in the VRM.
The value of the input capacitor is determined from the
maximum channel current and the highest switching
frequency of the power stage. The input capacitor to the
VRM is implemented using electrolytic capacitors. The ESR
and ESL of the input capacitor are not critical concerns
because the input current has low magnitude and tight
regulation is not required.
POWER IC V
CC
CAPACITOR:
A bank of input capacitors is also needed at the supply
terminals of each Power IC. The high-side FET in the buck
converter is integrated into the Power IC. The low-side FET
is an external part. The package inductance of the Power IC
and the low-side FET as well as the path inductance
between the two parts are parasitic elements in the power
stage. A large current slews through the parasitic inductance
each time the high side or the low-side FET is switched. This
results in high-voltage spikes and ringing at the switch node,
V
CC
pad and the ground pad. Under extreme
circumstances, the voltage spike may exceed the
breakdown voltage of the high side or the low-side FET.
Furthermore, the Power IC has low-voltage analog and
digital circuits that are isolated from the power stage.
Extreme swings of the high-side FET voltage beyond the
nominal values may exceed the limits of the isolation and
result in the undesired effects of latch-up, substrate current
and loss of synchronization with the digital controller. Power
supply stabilizing capacitors should be placed between the
V
CC
and ground planes at the site of each Power IC.
Ceramic capacitors that have low ESR and ESL are well
suited for this application. Similar to Figure 43, the ceramic
capacitors at each Power IC eliminate the need for the high-
current pulses to flow from the connector input pins to the
site of each Power IC, thus reducing on-board power
dissipation
Output Capacitors
The choice of the output capacitor depends on the desired
output voltage ripple, switching frequency of the power stage
and the transient voltage excursions. A combination of
OSCON and ceramic capacitors is used to form the output
capacitor bank.
Steady State Ripple
The fundamental ripple of a buck converter is ideally
determined by the value of the output inductor and the
output capacitor. The fundamental ripple of a multi-phase
buck converter operating at a switching frequency of several
hundred kilohertz can be shown to be negligible.
However, as the switching frequency increases, the
FIGURE 42. AVERAGE CURRENT PREDICTED FROM PEAK
CURRENT SAMPLE MINUS IOS OFFSET
High Side Current
Current
Average
VRM Input
FIGURE 43. INPUT CAPACITOR FILTERS OUT THE INPUT
CURRENT REQUIREMENT OF THE VRM AND
LIMITS THE SLEW RATE OF THE INPUT
CURRENT
ISL6580
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