參數(shù)資料
型號(hào): ISL6568IRZ-T
廠商: INTERSIL CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications
中文描述: SWITCHING CONTROLLER, 275 kHz SWITCHING FREQ-MAX, PQCC32
封裝: 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220-VHHD, QFN-32
文件頁(yè)數(shù): 15/28頁(yè)
文件大?。?/td> 716K
代理商: ISL6568IRZ-T
15
FN9187.3
July 25, 2005
Once the desired output offset voltage has been determined,
use the following formulas to set R
OFS
:
For Positive Offset (connect R
OFS
to GND):
×
OFFSET
For Negative Offset (connect R
OFS
to VCC):
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner, supervising a safe output voltage transition
without discontinuity or disruption.
The DAC mode the ISL6568 is operating in determines how
the controller responds to a dynamic VID change. When in
VRM10 mode the ISL6568 checks the VID inputs six times
every switching cycle. If a new code is established and it
stays the same for 3 consecutive readings, the ISL6568
recognizes the change and increments the reference.
Specific to VRM10, the processor controls the VID
transitions and is responsible for incrementing or
decrementing one VID step at a time. In VRM10 setting, the
ISL6568 will immediately change the reference to the new
requested value as soon as the request is validated; in
cases where the reference step is too large, the sudden
change can trigger overcurrent or overvoltage events.
In order to ensure the smooth transition of output voltage
during a VRM10 VID change, a VID step change smoothing
network is required for an ISL6568 based voltage regulator.
This network is composed of a 1k
internal resistor between
the output of DAC and the capacitor C
REF
, between the REF
pin and ground. The selection of C
REF
is based on the time
duration for 1 bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
bit every T
VID
, the relationship between C
REF
and T
VID
is
given by Equation 10.
As an example, for a VID step change rate of 5
μ
s per bit, the
value of C
REF
is 22nF based on Equation 10.
When running in VRM9 or AMD Hammer operation, the
ISL6568 responds slightly differently to a dynamic VID change
than when in VRM10 mode. In these modes the VID code can
be changed by more than a 1-bit step at a time. Once the
controller receives the new VID code it waits half of a phase
cycle and then begins slewing the DAC 12.5mV every phase
cycle, until the VID and DAC are equal. Thus, the total time
required for a VID change, t
DVID
, is dependent on the switching
frequency (f
S
), the size of the change (
V
VID
), and the time
required to register the VID change. The one-cycle addition in
the t
DVID
equation is due to the possibility that the VID code
change may occur up to one full switching cycle before being
recognized. The approximate time required for a ISL6568-
based converter in AMD Hammer configuration running at f
S
=
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
1.5V
GND
R
OFS
R
FB
VDIFF
ISL6568
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VREF
V
OFS
-
+
I
OFS
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
1.5V
VCC
R
OFS
R
FB
VDIFF
ISL6568
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VREF
V
OFS
+
-
I
OFS
(EQ. 8)
R
OFS
0.5
--------------------------
R
=
(EQ. 9)
R
OFS
1.5
OFFSET
R
×
--------------------------
=
C
REF
0.004X T
VID
=
(EQ. 10)
ISL6568
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