參數(shù)資料
型號(hào)： ISL6568CRZA
廠商： INTERSIL CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： Two-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9, VRM10, and AMD Hammer Applications
中文描述： SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PQCC32
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220-VHHD, MLFP, QFN-32
文件頁(yè)數(shù)： 18/28頁(yè)
文件大小： 716K
代理商： ISL6568CRZA
18
FN9187.3
July 25, 2005
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
ENLL, POR, or one of the no-CPU VID codes. If after an
undervoltage or overvoltage event occurs the output returns
to within under and overvoltage limits, PGOOD will return
high.
Undervoltage Detection
The undervoltage threshold is set at 82% of the VID code.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 85% of the VID code.
Overvoltage Protection
The ISL6568 constantly monitors the difference between the
VSEN and RGND voltages to detect if an overvoltage event
occurs. During soft-start, while the DAC is ramping up, the
overvoltage trip level is the higher of DAC plus 150mV or a
fixed voltage, V
OVP
. The fixed voltage, V
OVP
, is 1.67V when
running in AMD Hammer, or VRM10 modes, and 1.97V for
VRM9 mode. Upon successful soft-start, the overvoltage trip
level is only DAC plus 150mV. OVP releases 50mV below its
trip point if it was “DAC plus 150mV” that tripped it, and
releases 100mV below its trip point if it was the fixed voltage,
V
OVP
, that tripped it. Actions are taken by the ISL6568 to
protect the microprocessor load when an overvoltage
condition occurs, until the output voltage falls back within set
limits.
At the inception of an overvoltage event, all LGATE signals
are commanded high, and the PGOOD signal is driven low.
This causes the controller to turn on the lower MOSFETs
and pull the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high until
VDIFF falls to within the overvoltage limits explained above.
The ISL6568 will continue to protect the load in this fashion
as long as the overvoltage condition recurs.
Once an overvoltage condition ends the ISL6568 continues
normal operation and PGOOD returns high.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6568 is designed to protect the load from any overvoltage
events that may occur. This is accomplished by means of an
internal 10k
resistor tied from PHASE to LGATE, which
turns on the lower MOSFET to control the output voltage
until the overvoltage event ceases or the input power supply
cuts off. For complete protection, the low side MOSFET
should have a gate threshold well below the maximum
voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6568 is designed to detect this
and shut down the controller. This event is detected by
monitoring the voltage on the IREF pin, which is a local
version of V
OUT
sensed at the outputs of the inductors.
If VSEN or RGND become opened, VDIFF falls, causing the
duty cycle to increase and the output voltage on IREF to
increase. If the voltage on IREF exceeds “VDIFF+1V”, the
controller will shut down. Once the voltage on IREF falls
below “VDIFF+1V”, the ISL6568 will restart at the beginning
of soft-start.
Overcurrent Protection
The ISL6568 detects overcurrent events by comparing the
droop voltage, V
DROOP
, to the OCSET voltage, V
OCSET
, as
shown in Figure 13. The droop voltage, set by the external
current sensing circuitry, is proportional to the output current
FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY
-
+
VID + 150mV
VSEN
-
+
0.82 x DAC
OV
UV
PGOOD
SOFT-START, FAULT
AND CONTROL LOGIC
-
+
OC
-
+
ISEN
IREF
ISUM
ICOMP
OCSET
R
OCSET
+
-
V
DROOP
V
OCSET
+
-
V
OVP
100uA
ISL6568 INTERNAL CIRCUITRY
-
+
RGND
x1
-
+
+1V
VDIFF
ISL6568
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