參數(shù)資料
型號(hào)： ISL6567IRZ-T
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers
中文描述： SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PQCC24
封裝： 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220VGGD-2, QFN-24
文件頁數(shù)： 20/26頁
文件大?。?/td> 659K
代理商： ISL6567IRZ-T
20
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 23. Use the following guidelines for locating the
poles and zeros of the compensation network:
1. Select a value for R1 (1k
to 5k
, typically). Calculate
value for R2 for desired converter bandwidth (F
0
). If
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 24, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier, in order to compensate for the
attenuation introduced by the resistor divider, the
obtained R2 value needs be multiplied by a factor of
(R
P
+R
S
)/R
P
. The remainder of the calculations remain
unchanged, as long as the compensated R2 value is
used.
2. Calculate C1 such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
CE
/F
LC
, the lower the F
Z1
frequency (to maximize phase boost at F
LC
).
3. Calculate C2 such that F
P1
is placed at F
CE
.
4. Calculate R3 such that F
Z2
is placed at F
LC
. Calculate C3
such that F
P2
is placed below F
SW
(typically, 0.5 to 1.0
times F
SW
). F
SW
represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
P2
lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
MOD
), feedback
compensation (G
FB
) and closed-loop response (G
CL
):
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 25 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
P2
against the capabilities of the error
amplifier. The closed loop gain, G
CL
, is constructed on the
log-log graph of Figure 25 by adding the modulator gain,
G
MOD
(in dB), to the feedback compensation gain, G
FB
(in
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model presented
R2
V
R1 F
MAX
IN
LC
---------------------------------------------
=
C1
2
R2 0.5 F
LC
-----------------------------------------------
=
C2
2
π
R2 C1 F
CE
1
–
---------------------------------------------------------
=
R3
F
LC
------------
1
–
---------------------
=
C3
SW
-------------------------------------------------
=
G
MOD
f
( )
d
V
OSC
-----------------------------
1
s f
( )
E
D
+
(
)
C
s
2
f
( )
L C
+
+
-----------------------------+
=
G
FB
f
( )
s f
( )
R1
+
C1
C2
(
)
--------+
=
)
C3
1
s f
( )
R3 C3
+
(
)
1
s f
( )
R2
C2
--------+
+
----------------------------------+
G
CL
f
( )
G
MOD
f
( )
G
FB
f
( )
=
where s f
( )
2
π
=
F
Z1
-------------------------------
=
F
Z2
R3
)
C3
----------------------+
=
F
P1
2
π
R2
C1
+
C2
----------------------
----------------------------------------------
=
F
P2
-------------------------------
=
0
F
P1
F
Z2
OPEN LOOP E/A GAIN
F
Z1
F
P2
F
LC
F
CE
COMPENSATION GAIN
CLOSED LOOP GAIN
G
FREQUENCY
MODULATOR GAIN
FIGURE 25. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
20
d
OSC
V
IN
----V
log
20
R1
log
LOG
L
F
0
G
MOD
G
FB
G
CL
ISL6567
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