參數(shù)資料
型號(hào)： ISL6567IRZ-T
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers
中文描述： SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PQCC24
封裝： 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220VGGD-2, QFN-24
文件頁(yè)數(shù)： 10/26頁(yè)
文件大?。?/td> 659K
代理商： ISL6567IRZ-T
10
INTERLEAVING
The switching of each channel in a ISL6567-based converter
is timed to be symmetrically out of phase with the other
channel. As a result, the two-phase converter has a
combined ripple frequency twice the frequency of one of its
phases. In addition, the peak-to-peak amplitude of the
combined inductor currents is proportionately reduced.
Increased ripple frequency and lower ripple amplitude
generally translate to lower per-channel inductance and/or
lower total output capacitance for any given set of
performance specification.
Figure 3 illustrates the additive effect on output ripple
frequency. The two channel currents (I
L1
and I
L2
), combine
to form the AC ripple current and the DC load current. The
ripple component has two times the ripple frequency of each
individual channel current.
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
V
IN
and V
OUT
are the input and output voltages,
respectively, L is the single-channel inductor value, and f
S
is
the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Peak-to-peak ripple current
decreases by an amount proportional to the number of
channels. Output-voltage ripple is a function of capacitance,
capacitor equivalent series resistance (ESR), and inductor
ripple current. Reducing the inductor ripple current allows
the designer to use fewer or less costly output capacitors
(should output high-frequency ripple be an important design
parameter).
Another benefit of interleaving is the reduction of input ripple
current. Input capacitance is determined in a large part by
the maximum input ripple current. Multi-phase topologies
can improve overall system cost and size by lowering input
ripple current and allowing the designer to reduce the cost of
input capacitance. The example in Figure 4 illustrates input
currents from a two-phase converter combining to reduce
the total input ripple current.
Figure 28, part of the section entitled
Input Capacitor
Selection,
can be used to determine the input-capacitor
RMS current based on load current and duty cycle. The
figure is provided as an aid in determining the optimal input
capacitor solution.
PWM OPERATION
One switching cycle for the ISL6567 is defined as the time
between consecutive PWM pulse terminations (turn-off of
the upper MOSFET on a channel). Each cycle begins when
a switching clock signal commands the upper MOSFET to
go off. The other channel’s upper MOSFET conduction is
terminated 1/2 of a cycle later.
Once a channel’s upper MOSFET is turned off, the lower
MOSFET remains on for a minimum of 1/3 cycle. This forced
off time is required to assure an accurate current sample.
Following the 1/3-cycle forced off time, the controller enables
the upper MOSFET output. Once enabled, the upper
MOSFET output transitions high when the sawtooth signal
crosses the adjusted error-amplifier output signal, as
illustrated in Figure 2. Just prior to the upper drive turning
FIGURE 3. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 2-PHASE CONVERTER
PWM2
PWM1
I
L2
I
L1
I
L1
+ I
L2
I
L PP
V
------------–
V
L f
S
(
)
V
OUT
V
IN
=
I
PP
V
-------------------------------------------------------------------
N
S
V
–
(
)
V
IN
=
FIGURE 4. INPUT CAPACITOR CURRENT AND INDIVIDUAL
CHANNEL CURRENTS IN A 2-PHASE
CONVERTER
Q1 D-S CURRENT
Q3 D-S CURRENT
C
IN
CURRENT
ISL6567
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