參數(shù)資料
型號(hào)： ISL6567
廠(chǎng)商： Intersil Corporation
英文描述： Dual Low-Noise Wide-Bandwidth Precision Amplifier 8-SOIC -40 to 85
中文描述： 多用途兩相降壓PWM控制器集成MOSFET驅(qū)動(dòng)器
文件頁(yè)數(shù)： 18/26頁(yè)
文件大?。?/td> 659K
代理商： ISL6567
18
Figure 20 details the normalized maximum power dissipation
R
BIAS
will be subject to in the given application. To use the
graph provided, find the power dissipation level
corresponding to the minimum input voltage and the input
voltage range and multiply it by the maximum desired bias
current to obtain the maximum power R
BIAS
will dissipate.
Alternately, the maximum power dissipation inside R
BIAS
can be calculated using the following equation:
(
INMIN
VCC
Maximum power dissipation in the bias resistor will take
place at the upper end of the input voltage range. Select a
resistor with a power dissipation rating above the calculated
value and pay attention to design aspects related to the
power dissipation level of this component. Although Figures
18 through 20 assume a VCC voltage of 5V, the design aid
curves can be translated to a different VCC voltage by
translating them in the amount of the voltage differential, to
the left for a lower VCC voltage, or to the right for a higher
VCC voltage,
Should the simple series bias resistor configuration fall short
of providing the necessary bias current, the internal shunt
regulator can be used in conjunction with an external BJT
transistor to increase the shunt regulator current. Figure 21
details such an implementation utilizing a PNP transistor.
Selection of R1 can be based on the graphs provided for the
passive regulator configuration. Maximum power dissipation
inside Q1 will take place when maximum voltage is applied
to the circuit and the ISL6567 is disabled; determine
I
VREGMAX
by reverse-use of the graph in Figure 18 and use
the obtained number to calculate Q1 power dissipation.
An NPN transistor can also be used to increase the
maximum available bias current, as shown in Figure 22.
Used as a series pass element, Q1 will dissipate the most
power when the circuit is enabled and operational, and the
input voltage, V
IN
, is at its highest level.
With the series pass element configuration shown in
Figure 22, the difference between the input and the
regulation level at the VCC pin has to be higher than the
lowest acceptable V
CE
of Q1 (may choose to run Q1 into
saturation, but must consider the reduced gain). Thus, R2
has to be chosen such that it will provide appropriate base
current at lowest V
CE
of Q1. Next, ensure the ISL6567’s
I
VREGMAX
is not exceeded when the input voltage swings to
its highest extreme (assume base current goes to 0 when
the IC is disabled). R1 is an optional circuit element: it can
FIGURE 19. NORMALIZED RESISTOR VALUE IN PASSIVE
CONFIGURATION; V
VCC
= 5V
6
7
8
9
10
11
V
INmin
(V)
R
B
7
6
5
4
3
2
1
0
FIGURE 20. NORMALIZED RESISTOR POWER DISSIPATION
(AS SELECTED IN FIGURE 17) vs MINIMUM
INPUT VOLTAGE; V
VCC
= 5V
V
IN
= 1V
V
IN
= 2V
V
IN
= 3V
V
IN
= 4V
V
IN
= 5V
V
IN
= 6V
V
IN
= 7V
V
IN
= 8V
6
7
8
9
10
11
V
INmin
(V)
150
135
120
105
90
75
60
45
30
15
0
P
M
P
MAXRBIAS
V
------------------------–
I
BIAS
V
VCC
–
)
=
-
+
EXTERNAL CIRCUIT
ISL6567
SHUNT REGULATOR
E/A
POR
CIRCUIT
VREG
R1
V
IN
VREF
VCC
PVCC
Q1
FIGURE 21. INTERNAL SHUNT REGULATOR USE WITH
EXTERNAL PNP TRANSISTOR (ACTIVE
CONFIGURATION)
R2
(optional)
ISL6567
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ISL6567CRZ 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無(wú) 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR)
ISL6567CRZ-T 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無(wú) 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR)
ISL6567IRZ 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無(wú) 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR)
ISL6567IRZS2698 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無(wú) 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR)
ISL6567IRZ-T 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無(wú) 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR)
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