參數(shù)資料
型號(hào)： ISL6564A
廠商： Intersil Corporation
英文描述： Multiphase PWM Controller with Linear 6-Bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing
中文描述： 多相PWM控制器，帶有線性6位DAC能精密的RDS（ON）或DCR差分電流檢測(cè)
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 636K
代理商： ISL6564A
14
FN6285.1
March 20, 2007
MOSFET r
DS(ON)
SENSING
The controller can also sense the channel load current by
sampling the voltage across the lower MOSFET r
DS(ON)
(see Figure 6). The amplifier is ground-reference by
connecting the ISEN- input to the source of the lower
MOSFET. ISEN+ connects to the PHASE node through a
resistor R
ISEN
. The voltage across R
ISEN
is equivalent to
the voltage drop across the r
DS(ON)
of the lower MOSFET
while it is conducting. The resulting current into the ISEN+
pin is proportional to the channel current I
L
. The ISEN
current is then sampled and held after sufficient settling time.
The sampled current I
n
, is used for channel-current balance,
load-line regulation, and overcurrent protection. From
Figure 6, Equation 7 for I
SEN
is derived.
where I
L
is the channel current. Since MOSFET r
DS(ON)
increases with temperature, a PTC resistor should be
chosen for R
ISEN
to compensate for this change.
Channel-Current Balance
The sampled currents I
n
, from each active channel are
summed together and divided by the number of active
channels. The resulting cycle average current I
AVG
, provides
a measure of the total load current demand on the converter
during each switching cycle. Channel current balance is
achieved by comparing the sampled current of each channel
to the cycle average current, and making an appropriate
adjustment to each channel pulse width based on the error.
Intersil’s patented current-balance method is illustrated in
Figure 7, with error correction for channel 1 represented. In
the figure, the cycle average current combines with the
channel 1 sample, I
1
, to create an error signal I
ER
. The
filtered error signal modifies the pulse width commanded by
V
COMP
to correct any unbalance and force I
ER
toward zero.
The same method for error signal correction is applied to
each active channel.
Channel current balance is essential in realizing the thermal
advantage of multiphase operation. The heat generated in
down converting is dissipated over multiple devices and a
greater area. The designer avoids the complexity of driving
multiple parallel MOSFETs, and the expense of using heat
sinks and nonstandard magnetic materials.
Voltage Regulation
The integrating compensation network shown in Figure 8
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6564A to include the
combined tolerances of each of these elements.
The output of the error amplifier, V
COMP
, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
voltage. The internal and external circuitry which control
voltage regulation is illustrated in Figure 8.
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
I
n
ISEN
IL
RISEN
=
-
+
ISEN-(n)
SAMPLE
&
HOLD
ISL6564A INTERNAL CIRCUIT
ISEN+(n)
R
ISEN(n)
R
SENSE
L
V
OUT
C
OUT
IL
FIGURE 6. MOSFET r
DS(ON)
CURRENT-SENSING CIRCUIT
I
n
ISEN
IL
(
)
rRISEN
=
-
+
ISEN+(n)
R
ISEN
(PTC)
SAMPLE
&
HOLD
ISL6564A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
V
IN
N-CHANNEL
MOSFETs
-
ILrDS ON
+
)
I
L
ISEN-(n)
I
SEN
I
L
r
ISEN
)
-R
=
(EQ. 7)
FIGURE 7. CHANNEL 1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
÷
N
I
AVG
I
4
*
I
3
*
I
2
Σ
-
+
+
-
+
-
f(j
ω
)
PWM1
I
1
V
COMP
SAWTOOTH SIGNAL
I
ER
NOTE: *Channels 3 and 4 are optional.
FILTER
ISL6564A
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