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參數(shù)資料
| 型號(hào)： | ISL6535 |
| 廠商： | Intersil Corporation |
| 英文描述： | Synchronous Buck Pulse-Width Modulator (PWM) Controller |
| 中文描述： | 同步降壓脈寬調(diào)制（PWM）控制器 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 397K |
| 代理商： | ISL6535 |
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10
FN9255.0
January 17, 2006
2. Calculate C
1
such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor below
to the desired number). The higher the quality factor of the
output filter and/or the higher the ratio F
CE
/F
LC
, the lower
the F
Z1
frequency (to maximize phase boost at F
LC
).
2
LC
3. Calculate C
2
such that F
P1
is placed at F
CE
.
C
2
1
CE
4. Calculate R
3
such that F
Z2
is placed at F
LC
. Calculate C
3
such that F
P2
is placed below F
SW
(typically, 0.3 to 1.0
times F
SW
). F
SW
represents the switching frequency of the
regulator. Change the numerical factor (0.7) below to reflect
desired placement of this pole. Placement of F
P2
lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant duty
cycle jitter.
R
LC
3
SW
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
MOD
), feedback
compensation (G
FB
) and closed-loop response (G
CL
):
OSC
1
s f
( )
+
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 8 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
P2
against the capabilities of the error
amplifier. The closed loop gain, G
CL
, is constructed on the
log-log graph of Figure 8
by adding the modulator gain,
G
MOD
(in dB), to the feedback compensation gain, G
FB
(in
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model
presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover frequencies
in the range of 10% to 30% of the switching frequency,
F
SW
.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
C
1
----------------------------------------------
=
C
2
1
–
-------------------------------------------------------
=
R
3
------------
1
–
---------------------
=
C
3
------------------------------------------------
=
G
MOD
f
( )
D
V
------------------------------
ESR
DCR
+
(
)
C
s
2
f
( )
L C
+
----------------------------------+
=
G
FB
f
( )
1
s f
( )
R
C
1
+
C
1
C
2
(
)
--------+
=
1
s f
( )
R
R
+
(
)
C
+
1
s f
( )
R
3
C
3
+
(
)
1
s f
( )
R
2
2
1
C
2
---------+
+
-------------------------------------------------------------------------------------------------------------------------
G
CL
f
( )
G
MOD
f
( )
G
FB
f
( )
=
where s f
( )
2
π
=
F
Z1
2
1
------------------------------
=
F
Z2
1
R
3
)
C
3
-----------------------+
=
F
P1
2
π
R
2
2
1
+
C
2
--------------------
--------------------------------------------
=
F
P2
3
3
------------------------------
=
0
F
P1
F
Z2
OPEN LOOP E/A GAIN
F
Z1
F
P2
F
LC
F
CE
COMPENSATION GAIN
CLOSED LOOP GAIN
G
FREQUENCY
MODULATOR GAIN
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
20
OSC
V
IN
-------V
log
20
R1
log
LOG
L
F
0
G
MOD
G
FB
G
CL
ISL6535
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| ISL6535CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 16QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無(wú) 升壓:無(wú) 回掃:無(wú) 反相:無(wú) 倍增器:無(wú) 除法器:無(wú) Cuk:無(wú) 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
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