參數(shù)資料
型號(hào)： ISL6444
廠商： Intersil Corporation
英文描述： Dual PWM Controller with DDR Memory Option for Gateway Applications(帶DDR存儲(chǔ)器選項(xiàng)的網(wǎng)關(guān)專用雙PWM控制器)
中文描述： 雙PWM控制器的DDR網(wǎng)關(guān)應(yīng)用（帶的DDR存儲(chǔ)器選項(xiàng)的網(wǎng)關(guān)專用雙脈寬調(diào)制控制器內(nèi)存選項(xiàng)）
文件頁(yè)數(shù)： 7/19頁(yè)
文件大?。?/td> 372K
代理商： ISL6444
7
FN9069.3
April 12, 2007
Functional Pin Description
GND (Pin 1)
Signal ground for the IC.
LGATE1, LGATE2 (Pin 2, 27)
These are outputs of the lower MOSFET drivers.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers. These pins are connected to sources of the lower
MOSFETs of their respective converters.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
UGATE1, UGATE2 (Pin 5, 24)
These pins provide the gate drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect this pin to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. Anode of
the bootstrap diode is connected to the VCC pin.
ISEN1, ISEN2 (Pin 7, 22)
These pins are used to monitor the voltage drop across the
lower MOSFET for current feedback and overcurrent
protection. For precise current detection these inputs can be
connected to the optional current sense resistors placed in
series with the source of the lower MOSFETs.
EN1, EN2 (Pin 8, 21)
These pins enable operation of the respective converter
when high. When both pins are low, the chip is disabled and
only low leakage current <1μA is taken from VCC and VIN.
VOUT1, VOUT2 (Pin 9, 20)
These pins when connected to the converters’ respective
outputs provide the output voltage inside the chip to reduce
output voltage excursion during HYS/PWM transition. When
connected to ground, the se pins command forced
converters operate in continuous conduction mode at all
load levels.
VSEN1, VSEN2 (Pin 10, 19)
These pins are connected to the resistive dividers that set
the desired output voltage. The PGOOD, UVP, and OVP
circuits use this signal to report output voltage status.
OCSET1 (Pin 11)
A resistor from this pin to ground sets the over current
threshold for the first controller.
SOFT1, SOFT2 (Pin 12, 17)
These pins provide soft-start function for their respective
controllers. When the chip is enabled, the regulated 5
μ
A
pull-up current source charges the capacitor connected from
the pin to ground. The output voltage of the converter follows
the ramping voltage on the SOFT pin.
DDR (Pin 13)
This pin, when high, transforms dual channel chip into
complete DDR memory solution. The OCSET2 pin becomes
an input to provide the required tracking function. The
channel synchronization is changed from out-of-phase to
in-phase. The PG2/REF pin becomes the output of the
VDDQ/2 buffered voltage that is used as a reference voltage
by the second channel.
VIN (Pin 14)
Provides battery voltage to the oscillator for feed-forward
rejection of the input voltage variation.
When connected to ground via 100k
Ω
resistor while the
DDR pin is high, this pin commands the out-of-phase 90
o
channels synchronization for reduces inter-channel
interference.
PG1 (Pin 15)
PGOOD1 is an open drain output used to indicate the status
of the output voltage. This pin is pulled low when the first
channel output is not within
±10% of the set value.
PG2/REF (Pin 16)
This pin has a double function depending on the mode the
chip is operating. When the chip is used as a dual channel
PWM controller (DDR = 0), the pin provides a PGOOD2
function for the second channel. The pin is pulled low when
the second channel output is not within
±10% of the set value.
In DDR mode (DDR = 1), this pin serves as an output of the
buffer amplifier that provides VDDQ/2 reference voltage
applied to the OCSET2 pin.
OCSET2 (Pin 18)
In a dual channel application (DDR = 0), a resistor from this
pin to ground sets the over current threshold for the second
controller.
In the DDR application (DDR = 1), this pin sets the output
voltage of the buffer amplifier and the second controller and
should be connected to the center point of a divider from the
VDDQ output.
VCC (Pin 28)
This pin powers the controller.
ISL6444
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參數(shù)描述
ISL6444CA 功能描述:電流型 PWM 控制器 Dual with DDR Memory RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時(shí)間: 下降時(shí)間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14
ISL6444CA-T 功能描述:IC CONTROLLER DDR 28-QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR)
ISL6444CAZ 功能描述:IC CONTROLLER DDR 28-QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:43 系列:- 應(yīng)用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-QFN（7x7） 包裝:管件
ISL6444CAZT 制造商:Intersil Corporation 功能描述:
ISL6444CAZ-T 功能描述:IC CONTROLLER DDR 28-QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 標(biāo)準(zhǔn)包裝:43 系列:- 應(yīng)用:控制器，Intel VR11 輸入電壓:5 V ~ 12 V 輸出數(shù):1 輸出電壓:0.5 V ~ 1.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-QFN（7x7） 包裝:管件
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