參數(shù)資料
型號： ISL6308
廠商： Intersil Corporation
英文描述： Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
中文描述： 三相降壓PWM控制器，帶有高電流集成MOSFET驅(qū)動器
文件頁數(shù)： 19/27頁
文件大?。?/td> 765K
代理商： ISL6308
19
FN9208.2
October 19, 2005
In Equations 20 and 21, P
Qg_Q1
is the total upper gate drive
power loss and P
Qg_Q2
is the total lower gate drive power
loss; the gate charge (Q
G1
and Q
G2
) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
Q
is the driver total
quiescent current with no load at both drive outputs; N
Q1
and N
Q2
are the number of upper and lower MOSFETs per
phase, respectively; N
PHASE
is the number of active
phases. The I
Q*
VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW
at
300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P
DR_UP
, the lower drive path resistance,
P
DR_UP
, and in the boot strap diode, P
BOOT
. The rest of the
power will be dissipated by the external gate resistors (R
G1
and R
G2
) and the internal gate resistors (R
GI1
and R
GI2
) of
the MOSFETs. Figures 15 and 16 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P
DR
, can be roughly
estimated as:
Current Balancing Component Selection
The ISL6308 senses the channel load current by sampling
the voltage across the lower MOSFET r
DS(ON)
, as shown in
Figure 17. The ISEN pins are denoted ISEN1, ISEN2, and
ISEN3. The resistors connected between these pins and the
respective phase nodes determine the gains in the channel
current balance loop.
Select values for these resistors based on the room
temperature r
DS(ON)
of the lower MOSFETs; the full load
operating current, I
FL
; and the number of phases, N using
Equation 23.
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components
of one or more channels are inhibited from effectively
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
P
Qg_TOT
P
Qg_Q1
P
Qg_Q2
I
Q
VCC
+
+
=
(EQ. 20)
P
Qg_Q1
3
2
--
Q
G1
PVCC F
SW
N
Q1
N
PHASE
=
P
Qg_Q2
Q
G2
PVCC F
SW
N
Q2
N
PHASE
=
I
DR
3
2
--
Q
G1
N
Q1
Q
G2
N
Q2
+
N
PHASE
F
SW
I
Q
+
=
(EQ. 21)
Q1
D
S
G
R
GI1
R
G1
BOOT
R
HI1
C
DS
C
GS
C
GD
R
LO1
PHASE
PVCC
UGATE
PVCC
Q2
D
S
G
R
GI2
R
G2
R
HI2
C
DS
C
GS
C
GD
R
LO2
LGATE
P
DR
P
DR_UP
P
DR_LOW
P
BOOT
I
Q
VCC
(
)
+
+
+
=
(EQ. 22)
P
DR_UP
R
+
R
HI1
R
EXT1
--------------------------------------
R
+
R
LO1
R
EXT1
---------------------------------------
+
P
---------------------
=
P
DR_LOW
R
+
R
HI2
R
EXT2
--------------------------------------
R
+
R
LO2
R
EXT2
---------------------------------------
+
P
2
---------------------
=
R
EXT1
R
G1
R
Q1
-------------
+
=
R
EXT2
R
G2
R
Q2
-------------
+
=
P
BOOT
P
---------------------
=
R
ISEN
r
50 10
6
)
–
-----------------------
I
--N
=
(EQ. 23)
FIGURE 17. ISL6308 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY
ISEN(n)
R
ISEN
V
IN
CHANNEL N
UPPER MOSFET
CHANNEL N
LOWER MOSFET
-
+
IL
x
rDS ON
(
)
I
L
ISL6308
ISL6308
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