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參數(shù)資料
| 型號(hào)： | ISL6271ACRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Integrated XScale Regulator |
| 中文描述： | 0.8 A SWITCHING REGULATOR, PQCC20 |
| 封裝： | 4 X 4 MM, PLASTIC, MO-220-VGGD, QFN-20 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 588K |
| 代理商： | ISL6271ACRZ |
9
FN9171.1
Soft-Start and Slew Rate Control
To assure stability and minimize overshoot at start-up and
during DVM transitions, the ISL6271A implements a
controlled rise time of each regulator output. The Slew Rate
control bits in Table 2 are used to route one of 4 current
sources to the SOFT pin. These current sources along with
the soft-start capacitor will control the rate of rise of voltage
during DVM transitions. The recommended 10nF soft-start
capacitor will result in a typical slew rate of 1mV/μs at start-
up and the programmable DVM slew rates defined in
Table 2. Slower or faster start-up and DVM transactions can
be accommodated by selecting a smaller or larger soft-start
capacitor. By default bits D5 and D4 are set to “01”
corresponding to a SS current of 10μA. Writing “00” will
result in a 5μA of current whereas “10” corresponds to 24μA
and “11” corresponds to a typical source current of 47μA.
The expression i = cdv/dt can be used to solve for the
appropriate slew rate.
Example: Desired slew rate = 10mV/μs fixed slew rate and
the slew rate control bits are set to “11”. Then:
Isource = I
11
= 47μA (nominal), therefore
NOTE: Intel specifies a maximum slew rate for Vcore transitions. To
satisfy this requirement, the SS capacitor and SOFT pin sink/source
current tolerances must be considered. Refer to the Electrical
Specification table and appropriate Intel documents for details. Note
that when D5 and D4 are set to “11” the maximum source current is
64μA. Under this condition, the slew rate would be 16mV/μs if a
4.7nF SS capacitor varied by 15% negative. For this reason a 6.8nF
capacitor is recommended when D5 and D4 are set to “11”.
Undervoltage and Overvoltage on Vout
If the output voltage of the switching regulator exceeds 114%
of the SOFT pin voltage (programmed DAC voltage) for
longer than 1.5μs, an overvoltage fault will be tripped and
the phase node will be three-stated. Hysteresis requires the
voltage to fall to 106% before the fault is automatically reset.
An undervoltage occurs when the output voltage falls below
86% of SOFT pin voltage. Once this fault is triggered,
hysteresis sets the reset point to 94%. An undervoltage
condition will occur if the output DC current plus the ripple
exceeds the current limit point for a period longer than the
output capacitance hold-up time.
Loop Compensation
All three regulators are internally compensated for stability;
however, an external resistor connected between the core
regulator output and the FB pin can be used to alter the
closed loop gain of the switching regulator and optimize
transient response for a given output filter selection. The
following combinations of component values are
recommended:
Overcurrent Limit
To protect against an overcurrent condition, the core
regulator employs a proprietary current sensing circuit that
monitors the voltage drop across the internal upper
MOSFET. When an overcurrent condition is detected the
controller will limit the output current and if the condition
persists, the output voltage level will drop below the
undervoltage level tripping the PGOOD indicator. See
“Applications section” for details.
SRAM and PLL LDOs
The two linear regulators on the ISL6271A are designed to
satisfy the power requirements of the SRAM and phase-lock
loop circuitry internal to XScale processors. These
regulators share a common input voltage pin (LVCC) that
can be tied to the main battery PVCC or preferably to a lower
system voltage to effect a higher conversion efficiency. It is
recommended that LVCC be connected to pre-regulated
voltages between 1.8V - 2.5V.
Each LDO is internally compensated and designed to
operate with a low-ESR ceramic capacitor (X5R or better)
between 2.2μF and 3.3μF. Both LDOs have overcurrent,
undervoltage and thermal protection and share a common
enable signal (EN) with the core regulator, allowing them to
be enabled/disabled together as required by the processor.
BFLT#
The logic state of the BFLT# output indicates whether the
main battery input is adequate to power the system in
normal operation. A battery low (or absent) condition is
indicated by this pin being pulled low. Upon initial application
of battery power, it will indicate a battery good condition
when the battery voltage is greater than 2.8V (nominal), and
it will sustain the battery good indication until the voltage
drops below 2.6V (nominal). The output is pulled actively
low, with no main battery connected by tapping power from
the secondary input, BBAT. It is actively driven to BBAT
when the main battery is within the POR thresholds.
TABLE 2. SLEW RATE-SET BIT
I
2
C DATA BYTE
RATE
mV/μs
D5
D4
X
X
0
0
X
X
X
X
0.5
X
X
0
1
X
X
X
X
1
X
X
1
0
X
X
X
X
2.5
X
X
1
1
X
X
X
X
5
(EQ. 1)
C
dt
------
---------------------
=
A
----------------
----------------
4.7nF
=
=
TABLE 3. RECOMMENDED KEY COMPONENT VALUES FOR
CORE REGULATOR
LO
COUT
RCOMP
3.3μH
4.7μF
100k
4.7μH
10μF
50k
ISL6271A
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| ISL6271ACRZ-T | Integrated XScale Regulator |
| ISL6271A | Integrated XScale Regulator |
| ISL6271ACR | Integrated XScale Regulator |
| ISL6271ACR-T | Integrated XScale Regulator |
| ISL6293 | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6271ACRZ-T | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| ISL6271AEVAL1 | 功能描述:EVALUATION BOARD FOR ISL6271A RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - DC/DC 與 AC/DC（離線）SMPS 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:True Shutdown™ 主要目的:DC/DC，步升 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:- 電流 - 輸出:1A 輸入電壓:2.5 V ~ 5.5 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):升壓 頻率 - 開關(guān):3MHz 板類型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6271CR | 制造商:Rochester Electronics LLC 功能描述:PLL & SRAM REGULATOR FOR INTEL PROCESSORS - Bulk 制造商:Intersil Corporation 功能描述: |
| ISL6271EVAL1 | 制造商:Intersil Corporation 功能描述:ISL6271, PLL & SRAM REGULATOR FOR INTEL PROCESSORS EVALUATIO - Bulk |
| ISL6273 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1.2A Low Quiescent Current 1.5MHz High Efficiency Synchronous Buck Regulator |
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