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參數(shù)資料
| 型號(hào)： | ISL6271A |
| 廠(chǎng)商： | Intersil Corporation |
| 英文描述： | Integrated XScale Regulator |
| 中文描述： | 綜合Xscale的調(diào)節(jié) |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 588K |
| 代理商： | ISL6271A |
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14
FN9171.1
Measured Core Voltage Conversion Efficiency
The actual efficiency of the ISL6271A switching regulator is
illustrated in Figure 3 from 10mA to 800mA. The curves were
taken at room temperature using the ISL6271A evaluation
board. The output inductor used is an ultralow profile,
drumcore device with a DCR of 100m
.
Thermal Management
Although the ISL6271A is characteristically a low heat
generator, it will generate some heat as a result of the
inefficiencies in power conversion. The worst-case internal
power dissipation should be less than 250mW, translating
into a 11°C rise in junction temperature above ambient. If the
temperature of the chip does exceed 150° ±10°C as a result
of a high ambient temperature, the controller will disable the
outputs until the temperature decreases by 45°C.
Powering Intel XScale Processors
Intel identifies ten power domains required for powering
XScale processors. Of these ten power domains or voltages,
many may be strapped together as in Figure 25 and supplied
by a single regulator. These voltages however must be
applied systematically to the processor and two pins,
SYS_EN and PWR_EN facilitate this power sequence. The
PWR_EN pin is dedicated to enabling the CORE, PLL and
SRAM power domains and should be connected to the
ISL6271A enable pin. The SYS_EN pin is responsible for
enabling the system regulator. Figure 25 illustrates one
possible configuration using the Intersil EL7536 to power five
of the 10 domains.
NOTE: Intel warns that an improper power sequence can damage
the processor. Refer to the appropriate Intel applications material to
ensure proper voltage sequencing.
Design Notes
Refer to Table 3, "RECOMMENDED KEY COMPONENT
VALUES FOR CORE REGULATOR".
1. Do not leave pins VID2(5) or pin VID3(6) floating when
using the I
2
C bus. Tie these pins to GND (16).
2. Make sure that load current on VOUT returns to the pin 7
(PGND). Pin 16 (GND) functions as a quiet return for the
LVCC loads. Tie Pin 16 to Pin 7 at a single point as in
Figure 19.
3. Select the output capacitor for VSRAM and VPLL as
follows: 2.2μF<C8, C5<4.7μF, X5R.
4. BFLT# is internally pulled up to BBAT. Do not pullup to
any other external voltage.
5. The I
2
C pull-up resistors will affect standby leakage
power. A typical value to accommodate the I
2
C bus slew
rate requirements in “Standard Mode” is 5K.
6. Set the soft-start capacitor to 10nF to implement a
1mV/μs slew rate of the output voltage at startup. For
max slew rate, use 6.8nF soft-start capacitor.
7. Tie PGOOD to the XScale nVDD_fault pin.
8. Tie the BFLT# pin to the XScale nBatt_fault pin. The
BFLT# pin is pulled up internally to BBAT. A valid BFLT#
state under all conditions can be achieve by connecting
BBAT to the system BACK-UP battery. Otherwise,
consider the system start-up/shut-down voltage timing to
determine what system voltage that BBAT can be tied to
that will ensure the correct BFLT# operation. Current
drain on BBAT is much less than 1μA.
9. It is a good design practice to isolate PVCC from VCC
with a low pass filter (LPF) made up of a 10
resistor and
0.1μF ceramic capacitor. Ensure that VCC is kept within
0.3V of PVCC to avoid turning on internal protection
diodes.
10mV RIPPLE
IN DCM
CCM
RIPPLE
FIGURE 24. DCM TO CCM MODE TRANSITION
FIGURE 25. XSCALE POWER DOMAINS
VCC_USB
VCC_MEM
VCC_LCD
VCC_IO
VCC_BB
INTEL
Xscale
μP
EL7536
3.3V
OUTPUT
REGULATOR
EN
VCC_PLL
I
2
C_SDA
nVDD_FLT
nBatt_FLT
VCC_CORE
VCC_SRAM
I
2
C_SCL
SYS_EN
PWR_EN
SINGLE
CELL
TOTAL POWER SOLUTION
(INTEL XScale PROCESSOR)
VCC_USIM
BATT
TO
3V LDO
VCC_BATT
MOS
SWITCH
ISL6271A
PMIC
EN
ISL6271A
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| ISL6293-2CR | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6271ACR | 功能描述:IC REG PMIC 1BUCK 2LDO 20-QFN RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 電源管理 - 專(zhuān)用 系列:- 應(yīng)用說(shuō)明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:37 系列:- 應(yīng)用:醫(yī)療用超聲波成像，聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-TQFN-EP（8x8） 包裝:管件 |
| ISL6271ACR-T | 功能描述:IC PMIC XSCALE PROCESSOR 20-QFN RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 電源管理 - 專(zhuān)用 系列:- 應(yīng)用說(shuō)明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:37 系列:- 應(yīng)用:醫(yī)療用超聲波成像，聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-TQFN-EP（8x8） 包裝:管件 |
| ISL6271ACRZ | 功能描述:直流/直流開(kāi)關(guān)調(diào)節(jié)器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開(kāi)關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| ISL6271ACRZ-T | 功能描述:直流/直流開(kāi)關(guān)調(diào)節(jié)器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開(kāi)關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| ISL6271AEVAL1 | 功能描述:EVALUATION BOARD FOR ISL6271A RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - DC/DC 與 AC/DC（離線(xiàn)）SMPS 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:True Shutdown™ 主要目的:DC/DC，步升 輸出及類(lèi)型:1，非隔離 功率 - 輸出:- 輸出電壓:- 電流 - 輸出:1A 輸入電壓:2.5 V ~ 5.5 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):升壓 頻率 - 開(kāi)關(guān):3MHz 板類(lèi)型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
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