參數(shù)資料
型號： ISL6130
廠商： Intersil Corporation
英文描述： Power Sequencing Controllers
中文描述： 電源順序控制器
文件頁數(shù)： 5/21頁
文件大?。?/td> 488K
代理商： ISL6130
5
FN9005.8
February 5, 2007
Absolute Maximum Ratings
Thermal Information
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+6V
ISL6125 LOGIC OUT. . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to V
DD
+0.3V
RESET#, DLY_ON, DLYOFF. . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
Operating Conditions
V
DD
Supply Voltage Range . . . . . . . . . . . . . . . . . . . .+1.5V to +5.5V
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Notes 1, 2)
4 x 4 QFN Package . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .+125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . .+300°C
(QFN - Leads Only)
θ
JA
(°C/W)
48
θ
JC
(°C/W)
9
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
V
DD
= 1.5V to +5V, T
A
= T
J
= -40°C to +85°C, unless otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLO
Falling Undervoltage Lockout Threshold
V
UVLOvth
T
J
= +25°C
619
633
647
mV
Undervoltage Lockout Threshold Tempco
TC
UVLOvth
T
J
= -40°C to +85°C
40
nV/°C
Undervoltage Lockout Hysteresis
V
UVLOhys
10
mV
Undervoltage Lockout Threshold Range
RUVLOvth
Max V
UVLOvth
- Min V
UVLOvth
7
mV
Undervoltage Lockout Delay
TUVLOdel
ENABLE satisfied
10
ms
Transient Filter Duration
TFIL
V
DD
, UVLO, ENABLE glitch filter
30
μ
s
DELAY ON/OFF
Delay Charging Current
DLY_ichg
V
DLY
= 0V
0.92
1
1.08
μ
A
Delay Charging Current Range
DLY_ichg_r
DLY_ichg(max) - DLY_ichg(min)
0.08
μ
A
Delay Charging Current Temp. Coeff.
TC_DLY_ichg
0.2
nA/°C
Delay Threshold Voltage
DLY_Vth
1.238
1.266
1.294
V
Delay Threshold Voltage Temp. Coeff.
TC_DLY_Vth
0.2
mV/°C
ENABLE/ENABLE#, RESET# & SYSRST# I/O
ENABLE Threshold
V
ENh
1.2
V
ENABLE# Threshold
V
ENh
0.5 V
DD
V
ENABLE/ENABLE# Hysteresis
V
ENh -
V
ENl
Measured at V
DD
= 1.5V
0.2
V
ENABLE/ENABLE# Lockout Delay
TdelEN_LO
UVLO satisfied
10
ms
ENABLE/ENABLE# Input Capacitance
Cin_en
5
pF
RESET# Pull-up Voltage
Vpu_rst
V
DD
V
RESET# Pull-Down Current
I
RSTpd1
V
DD
= 1.5V, RST = 0.1V
5
mA
I
RSTpd3
V
DD
= 3.3V, RST = 0.1V
13
mA
I
RSTpd5
V
DD
= 5V, RST = 0.1V
17
mA
RESET# Delay after GATE High
T
RSTdel
GATE = V
DD
+5V
160
ms
RESET# Output Low
V
RSTl
Measured at V
DD
= 5V with 5k
pull-up resistors
0.1
V
RESET Output Capacitance
Cout_rst
10
pF
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
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