參數(shù)資料
型號(hào)： ISL54102CQZ
廠商： Intersil
文件頁(yè)數(shù)： 20/21頁(yè)
文件大小： 0K
描述： IC TMDS REGEN W/MUX 128MQFP
標(biāo)準(zhǔn)包裝： 66
應(yīng)用： 顯示器
接口： I²C
電源電壓： 3 V ~ 3.6 V
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-MQFP（14x20）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 1244 (CN2011-ZH PDF)
8
FN6275.5
June 4, 2008
Pin Descriptions
SYMBOL
DESCRIPTION
RX0-_A, RX0+_A, RX1-_A, RX1+_A,
RX2-_A, RX2+_A
TMDS Inputs. Incoming TMDS data signals for Channel A.
RX0-_B, RX0+_B, RX1-_B, RX1+_B,
RX2-_B, RX2+_B
TMDS Inputs. Incoming TMDS data signals for Channel B (ISL54100 and ISL54102 only).
RX0-_C, RX0+_C, RX1-_C, RX1+_C,
RX2-_C, RX2+_C
TMDS Inputs. Incoming TMDS data signals for Channel C (ISL54100 only).
RX0-_D, RX0+_D, RX1-_D, RX1+_D,
RX2-_D, RX2+_D
TMDS Inputs. Incoming TMDS data signals for Channel D (ISL54100 only).
RXC-_A, RXC+_A, RXC-_B, RXC+_B,
RXC-_C, RXC+_C, RXC-_D, RXC+_D
TMDS Inputs. Incoming TMDS clock signals for Channels A, B, C and D (ISL54100), Channels A and B
(ISL54102), or Channel A (ISL54101).
TX0-, TX0+, TX1-, TX1+, TX1-, TX1+
TMDS Outputs. TMDS output data for selected channel.
TXC-, TXC+
TMDS Outputs. TMDS output clock for selected channel.
SCL
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Note: Internal 65k
Ω pull-up to V
D.
SDA
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
Note: Internal 65k
Ω pull-up to V
D.
ADDR[6:0]
Digital inputs, 5V tolerant. 7-Bit address for serial interface.
Note: Internal 60k
Ω pull-down to GND.
CH_SEL_0, CH_SEL_1
Digital I/Os, 3.3V. Channel select inputs (for stand-alone operation), selected channel outputs (for
software configured or auto channel select modes).
CH_SEL_1 should be left unconnected for the ISL54102.
CH_SEL_0 and CH_SEL_1 should both be left unconnected for the ISL54101.
Note: The state of these outputs becomes random when the chip is in the Power-down mode.
AUTO_CH_SEL
Digital Input. Pull high to have the mux automatically select the highest channel (A is highest, D is lowest)
with an active TMDS clock. Low is manual channel select.
CHA_Active, CHB_Active,
CHC_Active, CHD_Active
Digital Outputs, 3.3V. Output goes high when there is an active TMDS clock on that channel's input. Used
for activity detect in a stand-alone configuration.
CHC_Active and CHD_Active are NC (do Not Connect) for the ISL54102.
CHB_Active, CHC_Active and CHD_Active are NC (do Not Connect) for the ISL54101.
RES_BIAS
Tie to GND through a 3.16k external resistor. Sets up internal bias currents.
RES_TERM
Tie to VD through a 1.0k 1% external resistor. During calibration, the termination resistor closest in value
to RES_TERM/20 (= 50
Ω) is selected.
PD
Digital Input, 3.3V. PD = Power-down. Pull high to put the ISL5410x in a minimum power consumption
mode.
Note: To ensure proper operation, this pin must be held low during power-up. It may be taken high 100ms
after the power supplies have settled to 3.3V ±10%.
When exiting Power-down, a termination resistor Recalibration cycle must be run to re-trim the
termination resistors (see register 0x03[7]).
Note: Internal 60k
Ω pull-down to GND.
RESET
Digital Input, 3.3V. Pull high then low to reset the mux. Tie to GND in final application.
Note: Internal 60k pull-down to GND.
TEST
Digital Input. Used for production testing only. Tie to GND in final application. This pin has an internal
pulldown to GND, so it is also acceptable to leave this pin floating.
VD
Power supply. Connect to a 3.3V supply and bypass each pin to GND with 0.1F.
VD_ESD
Power supply for ESD protection diodes. Connect one of these pins (pin 74 or 95) to the 3.3V VD supply
rail with a low VF (0.4V or lower) Schottky diode, with the cathode connected to VD_ESD and the anode
connected to VD. Bypass each pin to GND with 0.1F.
GND
Ground return for VD.
ISL54100, ISL54101, ISL54102
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