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參數(shù)資料
| 型號(hào)： | ISL54050IRUZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog Switch |
| 中文描述： | DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PQCC10 |
| 封裝： | 1.80 X 1.40 MM, 0.50 MM HEIGHT, ROHS COMPLIANT, MICRO, PLASTIC, MO-255, TQFN-10 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 277K |
| 代理商： | ISL54050IRUZ-T |
7
FN6356.1
March 28, 2007
Detailed Description
The ISL54050 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
on-resistance (0.29
Ω
) and high speed operation
(t
ON
= 40ns, t
OFF
= 20ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(4.5
μ
W max), low leakage currents (195nA max), and the tiny
μ
TQFN package. The ultra low on-resistance and r
ON
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1k
Ω
resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. R
ON
TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
ANALYZER
R
L
SIGNAL
GENERATOR
V+
C
0V or V+
NO or NC
COM
IN
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
V+
C
0V or V+
NO or NC
COM
IN
GND
V
NX
V
1
r
ON
= V
1
/100mA
100mA
Repeat test for all switches.
0V or V+
ANALYZER
V+
C
NO or NC
SIGNAL
GENERATOR
R
L
GND
IN
1
COM
50
Ω
N.C.
COM
NC or NO
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
V+
C
GND
NO or NC
COM
IN
IMPEDANCE
ANALYZER
0V or V+
Repeat test for all switches.
ISL54050
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