參數(shù)資料
型號： ISL5314INZ
廠商： INTERSIL CORP
元件分類： 數(shù)字信號處理外設(shè)
英文描述： Direct Digital Synthesizer
中文描述： 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP48
封裝： 7 X 7 MM, ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù)： 9/16頁
文件大?。?/td> 286K
代理商： ISL5314INZ
9
Address Hold Time, t
AH
Between ADDR and WR (Note 3)
0
-
-
ns
UPDATE Pulse Width, t
UW
(Note 3)
5
-
-
ns
UPDATE Setup Time, t
US
Between UPDATE and CLK (Note 3)
1
-
-
ns
UPDATE Hold Time, t
UH
Between UPDATE and CLK (Note 3)
3
-
-
ns
UPDATE Latency, t
UL
After UPDATE, before analog output change, if asserted after
writing to the control registers
-
14
-
Clock
Cycles
UPDATE Latency, t
UL
After UPDATE, before analog output change, if asserted before
writing to the control registers
-
11
-
Clock
Cycles
Maximum PH Rate
Rate of PH1 and PH0 pins (Note 3)
f
CLK
/2
-
-
Hz
Phase Pulse Width, t
PW
PH(1:0) (Note 3)
5
-
-
ns
Phase Setup Time, t
PS
Between PH(1:0) change and CLK (Note 3)
1
-
-
ns
Phase Hold Time, t
PH
Between PH(1:0) change and CLK (Note 3)
3
-
-
ns
Phase Latency, t
PL
Between PH(1:0) change and analog output change
-
12
-
Clock
Cycles
Maximum ENOFR Rate
Rate of ENOFR (Note 3)
f
CLK
/2
-
-
Hz
ENOFR Pulse Width, t
EW
ENOFR (Note 3)
5
-
-
ns
ENOFR Setup Time, t
ES
Between ENOFR and CLK (Note 3)
1
-
-
ns
ENOFR Hold Time, t
EH
Between ENOFR and CLK (Note 3)
3
-
-
ns
ENOFR Latency, t
EL
After ENOFR, before analog output change
-
14
-
Clock
Cycles
Write Enable Pulse Width, t
WR
WE (Note 3)
5
-
-
ns
Write Enable Setup Time, t
WS
Between WE and WR (Note 3)
2
-
-
ns
Write Enable Hold Time, t
WH
Between WE and WR (Note 3)
4
-
-
ns
RESET Pulse Width, t
RW
RESET (Note 3)
5
-
-
ns
RESET Setup Time, t
RS
Between RESET and CLK
1
-
-
ns
RESET Latency to Output, t
RL
After RESET, before analog output reflects reset values
-
11
-
Clock
Cycles
RESET Latency to Write, t
RE
After RESET, before the control registers can be written to
-
1
-
Clock
Cycles
Maximum SCLK Rate
See Figure 6 Timing Diagrams (Note 3)
50
-
-
MSPS
SCLK Pulse Width, t
SCW
See Figure 6 Timing Diagrams (Note 3)
5
-
-
ns
SDATA Pulse Width, t
SDW
See Figure 6 Timing Diagrams (Note 3)
5
-
-
ns
SDATA Setup Time, t
SDS
Between SDATA and SCLK. See Figure 6 Timing Diagrams. (Note
3)
6
-
-
ns
SDATA Hold Time, t
SDH
Between SDATA and SCLK. See Figure 6 Timing Diagrams. (Note
3)
1
-
-
ns
SSYNC Pulse Width, t
SSW
See Figure 6 Timing Diagrams (Note 3)
5
-
-
ns
SSYNC Setup Time, t
SSS
Between SSYNC and SCLK. See Figure 6 Timing Diagrams.
(Note 3)
6
-
-
ns
SSYNC Hold Time, t
SSH
Between SSYNC and SCLK. See Figure 6 Timing Diagrams.
(Note 3)
1
-
-
ns
Electrical Specifications
AV
DD
= DV
DD
= +5V (unless otherwise noted), V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= -40
o
C to 85
o
C for
all Min and Max Values. T
A
= 25
o
C for All Typical Values
(Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL5314
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