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參數(shù)資料
| 型號： | ISL5314INZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Direct Digital Synthesizer |
| 中文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 286K |
| 代理商： | ISL5314INZ |
4
where N = 1–5 (for 8–40 bit serial data) and f
CLK
is the DDS
clock rate. Three extra SCLKs are required (one for the SYNC
pulse plus two additional for register transfer). The latency in
seconds depends on how many bits of serial data are being
written and the speeds of both clocks. The center and offset
frequency registers cannot be written using the serial pins.
They must be programmed using the parallel interface.
In order to use the three wire serial interface in a mode that is
not the default mode, the parallel control bus must be used to
reprogram register 12. Register 12 can be set according to the
desired options of the serial interface that are described in the
register description table. Since the serial register defaults
enabled, it must be disabled in register 13 (bit 6) if it is not used.
Register 14
The parallel control bus must be used to program register 14
with 0x00h or 0x30h after assertion of RESET. See the Control
Register table in the back of the datasheet for more information.
Control Pins
There are three control pins provided for phase and frequency
control. The PH0 and PH1 pins select phase offsets of 0, 90,
180, and 270 degrees and can be used for low speed,
unfiltered BPSK or QPSK modulation. These pins can also be
used for providing sine/cosine when using two ISL5314s
together as quadrature local oscillators. The ENOFR pin
enables or zeros the offset frequency word to the phase
accumulator and can be used for FSK or MSK modulation.
These control pins and the UPDATE pin are passed through
special cells to minimize the probability of metastability. Writing
anything to register 15 behaves like an UPDATE so that the
user can save one control pin if desired.
Reset
A RESET pin is available which resets all registers to their
defaults. Register 14
must
always be written with 0x00h or
0x30h after a RESET. In order to reset the part, the user must
take the RESET pin low, allow at least one CLK rising edge,
and then take the RESET pin high again. The latency from
the RESET pin going high until the output reflects the reset
is eleven CLK cycles. See the register description table in
the back of the data sheet for the default states of all bits in
all registers. After RESET goes high, one rising edge of CLK
is required before the control registers can be written to
again. The center frequency register resets to f
CLK
/4. The
offset frequency register resets to an unknown frequency but
is disabled. The serial frequency register resets to an
unknown frequency and is enabled. If the serial register is
not used, disable it in register 13 using the parallel interface.
Comparator
A comparator is provided for square wave output generation.
The user can take the DDS analog output, filter it, and then
send it back into the comparator. A square wave will be
generated at the comparator output (COMPOUT pin) at an
amplitude level that is dependent on the digital power supply
(DV
DD
). The comparator was designed to operate at speeds
comparable to the DDS output frequency range (approximately
0–50MHz). It is not intended for low jitter applications (<0.5ns).
The comparator has a sleep mode that is activated by
connecting both inputs (IN- and IN+) to the analog power
supply plane. This will save approximately 4mA of current (as
shown in the Typical Application Circuit). If the comparator is
not used, leave the COMPOUT pin floating.
DAC Voltage Reference
The internal voltage reference for the DAC has a nominal
value of +1.2V with a
±
60ppm/
o
C drift coefficient over the
full temperature range of the converter. It is recommended
that a 0.1
μ
F capacitor be placed as close as possible to the
REFIO pin, connected to the analog ground. The REFLO pin
(11) selects the reference. The internal reference can be
selected if pin 11 is tied low (ground). If an external reference
is desired, then pin 11 should be tied high (the analog supply
voltage) and the external reference driven into REFIO, pin
12. The full-scale output current of the converter is a function
of the voltage reference used and the value of R
SET
. I
OUT
should be within the 2mA–20mA range, though operation
below 2mA is possible, with performance degradation.
If the internal reference is used, V
FSADJ
will equal
approximately 1.2V (pin 13). If an external reference is used,
V
FSADJ
will equal the external reference.
I
OUT
(Full Scale) = (V
FSADJ
/R
SET)
X 32.
TABLE 1. FREQUENCY CONTROL BIT ALIGNMENTS
48 Bits
(Individual Bit Alignment)
4444 4444
3333 3333
3322 2222
2222 1111
1111 1100
0000 0000
7654 3210
9876 5432
1098 7654
3210 9876
5432 1098
7654 3210
Phase Accumulator
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Center Frequency
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Offset Frequency
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Serial Frequency, 8 Bits
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Serial Frequency, 16 Bits
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
Serial Frequency, 24 Bits
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
Serial Frequency, 32 Bits
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
Serial Frequency, 40 Bits
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
ISL5314
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PDF描述 |
|---|---|
| ISL5314IN | Direct Digital Synthesizer |
| ISL5314 | Direct Digital Synthesizer |
| ISL5314EVAL2 | Direct Digital Synthesizer |
| ISL54048 | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch |
| ISL54048IRUZ-T | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL54000 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Integrated Audio Amplifier Systems |
| ISL54000IRTZ | 功能描述:IC AMP AUDIO PWR 1.23W AB 20TQFN RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻放大器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:DirectDrive® 類型:D 類 輸出類型:1-通道（單聲道），帶立體聲耳機 在某負載時最大輸出功率 x 通道數(shù)量:930mW x 1 @ 8 歐姆; 40mW x 2 @ 16 歐姆 電源電壓:2.7 V ~ 5.5 V 特點:消除爆音，差分輸入，I²C，靜音，關(guān)閉，音量控制 安裝類型:表面貼裝 供應(yīng)商設(shè)備封裝:25-WLP（2.09x2.09） 封裝/外殼:25-WFBGA，WLCSP 包裝:帶卷 (TR) 其它名稱:MAX97000EWA+T-ND |
| ISL54000IRTZ-T | 功能描述:IC AMP AUDIO PWR 1.23W AB 20TQFN RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻放大器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:DirectDrive® 類型:D 類 輸出類型:1-通道（單聲道），帶立體聲耳機 在某負載時最大輸出功率 x 通道數(shù)量:930mW x 1 @ 8 歐姆; 40mW x 2 @ 16 歐姆 電源電壓:2.7 V ~ 5.5 V 特點:消除爆音，差分輸入，I²C，靜音，關(guān)閉，音量控制 安裝類型:表面貼裝 供應(yīng)商設(shè)備封裝:25-WLP（2.09x2.09） 封裝/外殼:25-WFBGA，WLCSP 包裝:帶卷 (TR) 其它名稱:MAX97000EWA+T-ND |
| ISL54001 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Integrated Audio Amplifier Systems |
| ISL54001IRTZ | 功能描述:IC AMP AUDIO PWR 1.23W AB 20TQFN RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻放大器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:DirectDrive® 類型:D 類 輸出類型:1-通道（單聲道），帶立體聲耳機 在某負載時最大輸出功率 x 通道數(shù)量:930mW x 1 @ 8 歐姆; 40mW x 2 @ 16 歐姆 電源電壓:2.7 V ~ 5.5 V 特點:消除爆音，差分輸入，I²C，靜音，關(guān)閉，音量控制 安裝類型:表面貼裝 供應(yīng)商設(shè)備封裝:25-WLP（2.09x2.09） 封裝/外殼:25-WFBGA，WLCSP 包裝:帶卷 (TR) 其它名稱:MAX97000EWA+T-ND |
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