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參數(shù)資料
| 型號(hào)： | ISL5314 |
| 廠商： | Intersil Corporation |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Direct Digital Synthesizer |
| 中文描述： | 直接數(shù)字頻率合成器 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 809K |
| 代理商： | ISL5314 |
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5
I
OUT
(Full Scale) = (V
FSADJ
/R
SET)
X 32.
Analog Output
IOUTA and IOUTB are complementary current outputs. They
are generated by a 14-bit DAC that is capable of running at the
full 125MSPS rate. The DDS clock also clocks the DAC. The
sum of the two output currents is always equal to the full scale
output current minus one LSB. If single-ended use is desired, a
load resistor can be used to convert the output current to a
voltage. It is recommended that the unused output be equally
terminated. The voltage developed at the output must not
violate the output voltage compliance range of -1.0V to +1.25V.
R
LOAD
(the impedance loading each current output) should be
chosen so that the desired output voltage is produced in
conjunction with the output full scale current. If a known line
impedance is to be driven, then the output load resistor should
be chosen to match this impedance. The output voltage
equation is:
V
OUT
= I
OUT
X R
LOAD
.
These outputs can be used in a differential-to-single-ended
arrangement. This is typically done to achieve better harmonic
rejection. Because of a mismatch in IOUTA and IOUTB, the
transformer does not improve the harmonic rejection. However,
it can provide voltage gain without adding distortion. The SFDR
measurements in this data sheet were performed with a 1:1
transformer on the output of the DDS (see Figure 1). With the
center tap grounded, the output swing of pins 17 and 18 will be
biased at zero volts. The loading as shown in Figure 1 will result
in a 500mV
P-P
signal at the output of the transformer if the full
scale output current of the DAC is set to 20mA.
V
OUT
= 2 x I
OUT
x R
EQ
, where R
EQ
is 12.5
. Allowing the
center tap to float will result in identical transformer output,
however the output pins of the DAC will have positive DC
offset, which could limit the voltage swing available due to
the output voltage compliance range. The 50
load on the
output of the transformer represents the load at the end of a
‘transmission line’, typically a spectrum analyzer,
oscilloscope, or the next function in the signal chain. The
necessity to have a 50
impedance looking back into the
transformer is negated if the DDS is only driving a short
trace. The output voltage compliance range does limit the
impedance that is loading the DDS output.
Application Considerations
Ground Plane
Separate digital and analog ground planes should be used. All
of the digital functions of the device and their corresponding
components should be located over the digital ground plane
and terminated to the digital ground plane. The same is true for
the analog components and the analog ground plane. Pins 11
through 24 are analog pins, while all the others are digital.
Noise Reduction
To minimize power supply noise, 0.1
μ
F capacitors should be
placed as close as possible to the power supply pins, AV
DD
and DV
DD
. Also, the layout should be designed using
separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DV
DD
and to the analog ground for AV
DD
. Additional
filtering of the power supplies on the board is recommended.
Power Supplies
The DDS will provide the best SFDR (spurious free dynamic
range) when using +5V analog and +5V digital power
supply. The analog supply must always be +5V (
±
10%). The
digital supply can be either a +3.3V (
±
10%), a +5V (
±
10%)
supply, or anything in between. The DDS is rated to
125MSPS when using a +5V digital supply and 100MSPS
when using a +3.3V digital supply.
Improving SFDR
+5V power supplies provides the best SFDR. Under some
clock and output frequency combinations, particularly when
the f
CLK
/f
OUT
ratio is less than 4, the user can improve
SFDR even further by connecting the COMP2 pin (19) of the
DDS to the analog power supply. The digital supply must be
+5V if this option is explored. Improvements as much as
6dBc in the SFDR-to-Nyquist measurement were seen in the
lab.
FSK Modulation
Binary frequency shift keying (BFSK) can be done by using
the offset frequency register and the ENOFR pin. M-ary FSK
or GFSK (Gaussian) can be done by continuously loading in
new frequency words. The maximum FSK data rate of the
ISL5314 depends on the way the user programs the device
to do FSK, and the form of FSK.
For example, simple BFSK is efficiently performed with the
ISL5314 by loading the center frequency register with one fre-
quency, the offset frequency register with another frequency,
and toggling the ENOFR (enable offset frequency register)
pin. The latency is fourteen CLK cycles between assertion of
the ENOFR pin and the change occurring at the analog out-
put. However, the change in frequency can be pipelined such
that the ENOFR can be toggled at a rate up to
ENOFR
MAX
= f
CLK
/2,
where f
CLK
is the frequency of the master CLK.
PIN 17
PIN 18
100
ISL5314
50
50
50
FIGURE 1. TRANSFORMER OUTPUT CIRCUIT OPTION
IOUTB
IOUTA
V
OUT
= (2 x I
OUT
x R
EQ
)V
PP
R
EQ
IS THE IMPEDANCE
LOADING EACH OUTPUT
SPECTRUM ANALYZER
50
REPRESENTS THE
ISL5314
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL5314EVAL2 | Direct Digital Synthesizer |
| ISL54048 | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch |
| ISL54048IRUZ-T | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch |
| ISL54049 | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch |
| ISL54049IRUZ-T | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL5314_05 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Direct Digital Synthesizer |
| ISL5314EVAL2 | 制造商:Intersil Corporation 功能描述:DEV TOOL FOR COMMLINK DIRECT DGTL SYNTHESIZER - Bulk |
| ISL5314IN | 功能描述:IC SYNTHESIZER DIGITAL 48-MQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ISL5314INZ | 功能描述:IC SYNTHESIZER DIGITAL 48-MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ISL54000 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Integrated Audio Amplifier Systems |
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