- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383133 > ISL5217KIZ (INTERSIL CORP) Quad Programmable Up Converter PDF資料下載
參數(shù)資料
| 型號： | ISL5217KIZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, LEAD FREE, PLASTIC, BGA-196 |
| 文件頁數(shù)： | 5/43頁 |
| 文件大小： | 797K |
| 代理商： | ISL5217KIZ |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
5
FN6004.3
July 8, 2005
TXENA,
TXENB,
TXENC,
TXEND
I
Transmit Enable A-D. (TXENX) The processing channel selected for this enable will force a channel flush
(conditioned by control word 0x0c, bit 2), clear the data RAMs, and update the selected configuration registers upon
assertion. No additional requests for serial data will be made when TXENX is deasserted, unless conditioned by
control word 0x0c, bit 3. The polarity of TXENX is programmable. Optionally, TXENX can be internally generated
with a programmable duty cycle. Two different programmable TXENX cycles can be programmed and toggled
between based on programmed cycle length. See control word 0x0c, bit 11 and Table 43 for additional details.
UPDA, UPDB,
UPDC, UPDD
I
Update A-D. (UPDX) The processing channel selected for this input updates the selected configuration registers, if
the associated update mask bit is set. The polarity of UPDX is programmable.
SYNCO
O
Synchronization Output. The processing of multiple ISL5217 devices can be synchronized through software by
connecting the SYNCO of the master ISL5217 device to an UPDX pin of the ISL5217 slaves. The polarity of SYNCO
is programmable.
MODULATED DATA (80)
IOUT(19:0)
O
Output Data Bus A (19:0). Output bus A contains the digital modulated QUC output samples from Output
Summer/Formatter 1. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.
QOUT(19:0)
O
Output Data Bus B (19:0). The output bus contains the digital modulated QUC output samples from Output
Summer/Formatter 2. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.
IIN(19:0)
I/O
I Cascade In (19:0) or OUTPUT BUS C. Dual function I/O bus. The bus is configured for input when the output mode
is cascade in. The bus is configured for output for all other output modes.
I Cascade In. Input bus allows multiple parts to be cascaded by routing the digital modulated signal I CAS OUT,
(Bus A), from one QUC into Output Summer/Formatter 1 of a second QUC. I CAS IN (19:0) is in 2’s complement
format and is sampled on the rising edge of CLK. Bit<19> is the MSB.
Output Data Bus C. The output bus contains the digital modulated QUC output samples from Output
Summer/Formatter 3. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.
QIN(19:0)
I/O
Q Cascade in (19:0) or Output Data Bus D. Dual function I/O bus. The bus is configured for input when the output
mode is cascade in. The bus is configured for output for all other output modes.
Q Cascade in. Input bus allows multiple parts to be cascaded by routing the digital modulated signal Q CAS OUT,
(Bus B), from one QUC into Output Summer/Formatter 2 of a second QUC. Q CAS IN (19:0) is in 2’s complement
format and is sampled on the rising edge of CLK. Bit<19> is the MSB.
Output Data Bus D. The output bus contains the digital modulated QUC output samples from Output
Summer/Formatter 4. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB.
ISTRB
O
I data strobe. (active high). Used in the muxed I/Q mode. When asserted, the output data buses contain valid I data.
JTAG TEST ACCESS PORT
TMS
I
JTAG Test Mode Select. Internally pulled up.
TDI
I
JTAG Test Data In. Internally pulled up.
TCK
I
JTAG Test Clock.
TRST
I
JTAG Test Reset (Active Low). Internally pulled-up. This pin should be driven by the JTAG logic to obtain a TAP
controller reset, or if JTAG is not utilized, this pin should be tied to ground for normal operation. As recommended
in the 1149.1 standard documentation the TRST test pin should be made active soon after power-up to guarantee
a known state within the TAP logic on the ISL5217. This avoids potential damage due to signal contention at the
circuit’s inputs and outputs.
TDO
O
JTAG Test Data Out.
Pin Descriptions (all signals are active high unless otherwise stated)
(Continued)
NAME
TYPE
DESCRIPTION
ISL5217
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL5314INZ | Direct Digital Synthesizer |
| ISL5314IN | Direct Digital Synthesizer |
| ISL5314 | Direct Digital Synthesizer |
| ISL5314EVAL2 | Direct Digital Synthesizer |
| ISL54048 | Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPST Analog Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL5239 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Pre-Distortion Linearizer |
| ISL5239EVAL1 | 功能描述:EVALUATION BOARD FOR ISL5239 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| ISL5239KI | 功能描述:音頻 DSP PA LINEARIZER IND TEMP 1 0MM PITCH RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| ISL5239KIZ | 功能描述:音頻 DSP PA LINEARIZER IND 0MM PITCH BGA PACKAG RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| ISL5314 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Digital Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。