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| 型號： | ISL5217KIZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Quad Programmable Up Converter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, LEAD FREE, PLASTIC, BGA-196 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 797K |
| 代理商： | ISL5217KIZ |
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15
FN6004.3
July 8, 2005
The resulting complex output is given by the following
equations.
Re mixer (20:0) = I(20:0) * cos(18:0) - Q(20:0) * sin(18:0)
Im mixer (20:0) = Q(20:0) * cos(18:0) + I(20:0) * sin(18:0)
(Vector weighting for block diagram)
I (20:0) = 2
1
.. 2
-19
Q (20:0) = 2
1
... 2
-19
sin (18:0) = 2
0
... 2
-18
cos (18:0) = 2
0
... 2
-18
Re mixer(20:0) = 2
1
... 2
-19
Im mixer(20:0) = 2
1
... 2
-19
Output Processing
Output processing sums the modulated output of each
channel to provide multi-carrier outputs. There are four
4-channel summers, which combined with the outputs IOUT,
QOUT, and bidirectional outputs IIN and QIN can be
configured by the user to support eight output modes. The
output mode is determined by Device Control 0x78 bits 9:8
and Main Control 0xc, bit 7.
Output Modes
Cascade Mode: In this mode IIN<19:0> and QIN<19:0> are
configured as inputs for the real and imaginary cascade
inputs. This is the only mode where IIN and QIN are
configured as inputs.
The cascade input allows for more than four multi-channel
transmissions by summing the complex modulated signals
from other device’s with the four channel summer. A cascade
chain of four devices allows up to sixteen carriers. Each
device delays it’s 4-channel summation to align with the
cascade in from the previous device. Device Control 0x78
bits 2:1, Cascade delay <1:0>, identifies the position in the
cascade chain to select the appropriate delay. Device
Control 0x78, bit 3, Cascade input enable, zeroes the
cascade-in data when the port is not in use. The output of
the summation is saturated to prevent roll-over.
Real: Real data is output on IIN, QIN, IOUT, and QOUT.
Imag: Imaginary data is output on IIN, QIN, IOUT, and
QOUT.
Muxed I/Q: The output data alternates between real and
imaginary on clock time boundaries. The output signal
ISTRB is asserted when the output data is real. The ISTRB
is enabled by Device Control 0x78, bit 5. In this mode, the
I/Q samples are decimated by two. This is the only mode in
which the output data is decimated.
NOTE: When in Muxed I/Q mode the output order is I then
Q.
Muxed I/Q at 2x rate: The output data alternates between
real and imaginary within a clock time boundary. The output
data is real when the clock is high, and imaginary when the
clock is low. All I/Q samples are output, and there is no
decimation of the output stream. Care should be utilized to
ensure sufficient set-up time is achieved for the downstream
device in the application, as data is alternating I then Q
between clock boundaries.
Complex out 1: In this mode, complex data is output on IIN
and QIN, while real data is output on IOUT and QOUT.
Complex out 2: In this mode, real data is output on IIN and
QIN, while complex data is output on IOUT and QOUT.
Complex out 3: In this mode, complex data is output on IIN
and QIN and complex data is output on IOUT and QOUT.
TABLE 7. OUTPUT MODES
OUTPUT MODE
MAIN
CONTROL
0X0C, BIT 7
COMPLEX
OUTPUT
MODE
MAIN
CONTROL
0X78, BITS 9:8
OUTPUT
MODE
MAIN
CONTROL
0X78, BIT 10
OUTPUT 2X
SELECT
ISTRB CLK
IIN<19:0>
QIN<19:0>
IOUT<19:0>
QOUT<19:0>
Cascade Mode
0
00
0
X
X
Input re
Input im
re CASout
im CASout
Real
0
01
0
X
X
re SUM1
re SUM2
re SUM3
re SUM4
Imaginary
0
10
0
X
X
im SUM1
im SUM2
im SUM3
im SUM4
Muxed I/Q
0
11
0
1
X
re SUM1
re SUM2
re SUM3
re SUM4
0
11
0
0
X
im SUM1
im SUM2
im SUM3
im SUM4
Muxed I/Q at 2X Rate
0
01
1
X
1
re SUM1
re SUM2
re SUM3
re SUM4
0
01
1
X
0
im SUM1
im SUM2
im SUM3
im SUM4
Complex Output Mode 1 1 (Ch. 0 only)
01
0
X
X
re SUM1
im SUM1
re SUM3
re SUM4
Complex Output Mode 2 1 (Ch. 2 only)
01
0
X
X
re SUM1
re SUM2
re SUM3
im SUM3
Complex Output Mode 3 1 (Ch. 0 and 2)
01
0
X
X
re SUM1
im SUM1
re SUM3
im SUM3
NOTE: re CASout is re SUM1 + re CASinput, im CASout is im SUM1 + im CAS in.
ISL5217
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