參數(shù)資料
型號(hào)： ISL5216KI-1Z
廠商： INTERSIL CORP
元件分類： 無繩電話/電話
英文描述： Four-Channel Programmable Digital DownConverter
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-196
文件頁(yè)數(shù)： 13/65頁(yè)
文件大?。?/td> 1076K
代理商： ISL5216KI-1Z
13
July 8, 2005
Back End Data Routing
Back End Section
One back-end processing section is provided per channel.
Each back end section consists of a filter compute engine, a
FIFO/timer for evenly spacing samples (important when
implementing interpolation filters and resamplers), an AGC
and a cartesian-to-polar coordinate conversion block. A
block diagram showing the major functional blocks and data
routing is shown above. The data input to the back end
section is through the filter compute engine. There are two
other inputs to the filter compute engine, they are a data
recirculation path for cascading filters and a magnitude and
d
φ
/dt feedback path for AM and FM filtering. There are seven
outputs from each back end processing section. These are I
and Q directly out of the filter compute engine (I2, Q2), I and
Q passed through the FIFO and AGC multipliers (I1, Q1),
magnitude (MAG), phase (or d
φ
/dt), and the AGC gain
control value (GAIN). The I2/Q2 outputs are used when
cascading back end stages. The routing of signals within the
back end processing section is controlled by the filter
compute engine. The routing information is embedded in the
instruction bit fields used to define the digital filter being
implemented in the filter compute engine.
MAG: I
dphi/dt: Q
AGC
LOOP
FILTER
FILTER
COMPUTE
ENGINE
MUX
FIFO/
TIMER
AGC
MULT
CART
TO
POLAR
SHIFT
d/dt
M
U
X
x1, x2
x4, x8
M
U
X
FROM
CIC
PATH 0
PATH 2
(4:0)
I1
Q1
GAIN
MAG
PHASE
I2
Q2
DESTINATION BIT MAP
(BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD)
28
27
25 24 23 22 21 20 19 18
28
27
26, 25
24
23
22:18
AGC LOOP GAIN SELECT (PATH 01 ONLY)
UPDATE AGC LOOP (PATH 01 ONLY)
PATH 00 - - IMMEDIATE FILTER PROCESSOR FEEDBACK PATH
01 - - FIFO/AGC PATH TO I1 AND Q1
10 - - DIRECT OUT/CASCADE PATH TO I2 AND Q2
11 - - FIFO/AGC PATH TO I2 AND Q2
STROBE OUTPUT SECTION (START SERIAL OUTPUT WITH THIS SAMPLE)
FEED MAG/PHASE BACK TO FILTER PROCESSOR
FILTER PROCESSOR SEQUENCE STEP NUMBER
26
EXT AGC
GAIN
PATH 1
PATH 3
I2
Q2
ISL5216
相關(guān)PDF資料
PDF描述
ISL5216KIZ Four-Channel Programmable Digital DownConverter
ISL5216KI-1 Four-Channel Programmable Digital DownConverter
ISL5216KI Four-Channel Programmable Digital DownConverter
ISL5216 Four-Channel Programmable Digital DownConverter
ISL5217EVAL1 Quad Programmable Up Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISL5216KIZ 功能描述:上下轉(zhuǎn)換器 W/ANNEAL QD DIGTL DWNCNVRTR IND TEMP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
ISL5217 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Programmable Up Converter
ISL5217_05 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Programmable Up Converter
ISL5217EVAL1 功能描述:EVALUATION BOARD FOR ISL5217KI RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796
ISL5217KI 功能描述:上下轉(zhuǎn)換器 196BGA,-40+85C PROGRAMMABLE QUAD UP CONVERTER RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
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