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參數(shù)資料
| 型號： | ISL12008IB8Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 0K |
| 描述： | IC RTC I2C LO-POWER 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 980 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年 |
| 時(shí)間格式： | HH:MM:SS:hh（24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
4
FN6690.1
September 26, 2008
fSCL
SCL Frequency
400
kHz
tIN
Pulse width Suppression Time at SDA and
SCL Inputs
Any pulse narrower than the max
spec is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output Data Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window.
900
ns
tBUF
Time the Bus Must be Free Before the Start
of a New Transmission
SDA crossing 70% of VDD during
a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70%
of VDD window, to SCL rising edge
crossing 30% of VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
30% of VDD to SDA entering the
30% to 70% of VDD window.
20
900
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL
falling edge. Both crossing 70% of
VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1 x Cb
300
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
300
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-Up Resistor Off-Chip Maximum is determined by tR
and tF.
For Cb = 400pF, max is about
2k
Ω to~2.5kΩ.
For Cb = 40pF, max is about 15k
Ω
to ~20k
Ω.
1k
Ω
NOTES:
2. FT/OUT inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
5. Typical values are for T = +25°C and 3.3V supply voltage.
6. Limits should be considered typical and are not production tested.
7. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Serial Interface Specifications
Recommended Operating Conditions. Unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
(Note 5)
MAX
(Note 8)
UNITS NOTES
ISL12008
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| ISL12008IB8Z-T | 功能描述:實(shí)時(shí)時(shí)鐘 LW PWR RTC W/RESEAL 8LD RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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