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參數(shù)資料
| 型號： | IS61LPS102418A |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 256 × 72，為512k × 36，1024K × 18 18MB的同步流水線，單周期取消選擇靜態(tài)RAM |
| 文件頁數(shù)： | 1/34頁 |
| 文件大?。?/td> | 229K |
| 代理商： | IS61LPS102418A |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. D
02/11/05
ISSI
Copyright 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS61VPS25672A IS61LPS25672A
IS61VPS51236A IS61LPS51236A
IS61VPS102418A IS61LPS102418A
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Burst sequence control using MODE input
Three chip enable option for simple depth
expansion and address pipelining
Common data inputs and data outputs
Auto Power-down during deselect
Single cycle deselect
Snooze MODE for reduced-power standby
JTAG Boundary Scan for PBGA package
Power Supply
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%
JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball
PBGA, and 209-ball (x72) packages
Lead-free available
DESCRIPTION
The
ISSI IS61LPS/VPS51236A,IS61LPS/VPS102418A,
and IS61LPS/VPS25672A are high-speed, low-power syn-
chronous static RAMs designed to provide burstable, high-
performance memory for communication and networking
applications. The IS61LPS/VPS51236A is organized as
524,288 words by 36 bits, the IS61LPS/VPS102418A is
organized as 1,048,576 words by 18 bits, and the IS61LPS/
VPS25672A is organized as 262,144 words by 72 bits.
Fabricated with
ISSI's advanced CMOS technology, the
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through regis-
ters controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (
BWE) input combined with one or more
individual byte write signals (
BWx). In addition, Global
Write (
GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either
ADSP (Address Status
Processor) or
ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
256K x 72, 512K x 36, 1024K x 18
18Mb SYNCHRONOUS PIPELINED,
SINGLE CYCLE DESELECT STATIC RAM
FEBRUARY 2005
FAST ACCESS TIME
Symbol
Parameter
250
200
Units
tKQ
Clock Access Time
2.6
3.1
ns
tKC
Cycle Time
4
5
ns
Frequency
250
200
MHz
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PDF描述 |
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| IS61LPS12832A-200B2I | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS12832A-200B3 | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS12832A-200B3I | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS12832A-200TQ | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS12832A-200TQI | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LPS102418A-200B2 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS102418A-200B2I | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS102418A-200B3 | 功能描述:靜態(tài)隨機存取存儲器 18Mb,Pipeline,Sync,1Mb x 18,200MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LPS102418A-200B3I | 功能描述:靜態(tài)隨機存取存儲器 18Mb,Pipeline,Sync,1Mb x 18,200MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LPS102418A-200B3I-TR | 功能描述:靜態(tài)隨機存取存儲器 18Mb,Pipeline,Sync,1Mb x 18,200MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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