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參數(shù)資料
| 型號： | IS42LS16800A-10B |
| 英文描述： | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 16Meg × 8，8Meg x16 |
| 文件頁數(shù)： | 14/66頁 |
| 文件大?。?/td> | 556K |
| 代理商： | IS42LS16800A-10B |
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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
21
ADVANCEDINFORMATION
Rev. 00A
06/01/02
ISSI
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-7
-10
Symbol Parameter
Min.
Max.
Min.
Max
Units
tCK3
Clock Cycle Time
CAS Latency = 3
7
—
10
—
ns
tCK2
CAS Latency = 2
10
—
10
—
ns
tAC3
Access Time From CLK(4)
CAS Latency = 3
—
5.4
—
7
ns
tAC2
CAS Latency = 2
—
6
—
9
ns
tCHI
CLK HIGH Level Width
2.5
—
3.5
—
ns
tCL
CLK LOW Level Width
2.5
—
3.5
—
ns
tOH3
Output Data Hold Time
CAS Latency = 3
2.5
—
2.5
—
ns
tOH2
CAS Latency = 2
2.5
—
2.5
—
ns
tLZ
Output LOW Impedance Time
0
—
0
—
ns
tHZ3
Output HIGH Impedance Time(5)
CAS Latency = 3
—
6
—
7
ns
tHZ2
CAS Latency = 2
—
6
—
9
ns
tDS
Input Data Setup Time
1.5
—
2.0
—
ns
tDH
Input Data Hold Time
0.8
—
1
—
ns
tAS
Address Setup Time
.5
—
2.0
—
ns
tAH
Address Hold Time
0.8
—
1
—
ns
tCKS
CKE Setup Time
1.5
—
2.0
—
ns
tCKH
CKE Hold Time
0.8
—
1
—
ns
tCKA
CKE to CLK Recovery Delay Time
1CLK+3
—
1CLK+3
—ns
tCS
Command Setup Time (
CS, RAS, CAS, WE, DQM)
1.5
—
2.0
—
ns
tCH
Command Hold Time (
CS, RAS, CAS, WE, DQM)
0.8
—
1
—
ns
tRC
Command Period (REF to REF / ACT to ACT)
63
—
70
—
ns
tRAS
Command Period (ACT to PRE)
37
120,000
44
120,000
ns
tRP
Command Period (PRE to ACT)
15
—
18
—
ns
tRCD
Active Command To Read / Write Command Delay Time
15
—
18
—
ns
tRRD
Command Period (ACT [0] to ACT[1])
14
—
15
—
ns
tDPL3
Input Data To Precharge
CAS Latency = 3
2CLK
—
2CLK
—
ns
Command Delay time
tDPL2
CAS Latency = 2
2CLK
—
2CLK
—
ns
tDAL3
Input Data To Active / Refresh
CAS Latency = 3
CLK+tRP
—
2CLK+tRP
—ns
Command Delay time (During Auto-Precharge)
tDAL2
CAS Latency = 2
2CLK+tRP
—
2CLK+tRP
—ns
tT
Transition Time
0.5
30
0.5
30
ns
tREF
Refresh Cycle Time (4096)
—
64
—
64
ms
Notes:
1. When power is first applied, memory operation should be started 100 s after Vdd and VddQ reach their stipulated voltages.
Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL
(max.).
4. Access time is measured at 0.9V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)
when the output is in the high impedance state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42LS16800A-10BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS16800A-10T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS16800A-10TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS16800A-7B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS16800A-7BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
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