參數(shù)資料
型號(hào): IRS2336DPBF
廠商: International Rectifier
英文描述: HIGH VOLTAGE 3 PHASE GATE DRIVER IC
中文描述: 3相高壓柵極驅(qū)動(dòng)器集成電路
文件頁(yè)數(shù): 10/45頁(yè)
文件大?。?/td> 952K
代理商: IRS2336DPBF
IRS2336xD Family
www.irf.com
2007 International Rectifier
10
Dynamic Electrical Characteristics
V
CC
= V
B
= 15 V, V
S
= V
SS
= COM, T
A
= 25
C, and C
L
= 1000 pF unless otherwise specified.
Symbol
Definition
t
ON
Turn-on propagation delay
t
OFF
Turn-off propagation delay
t
R
Turn-on rise time
t
F
Turn-off fall time
Input filter time
(HIN, LIN, ITRIP & EN)
Enable low to output shutdown
propagation delay
t
FILTER,EN
Enable input filter time
FAULT clear time
RCIN: R = 2 M
, C = 1 nF
ITRIP to output shutdown
propagation delay
t
BL
ITRIP blanking time
t
FLT
ITRIP to FAULT propagation delay
DT
Deadtime
MDT
DT matching
Min
400
400
---
---
Typ
530
530
110
35
Max
750
750
190
75
Units
Test Conditions
t
FIL,IN
200
350
510
V
IN
= 0 V & 5 V
t
EN
350
440
650
V
IN,
V
EN
= 0 V or 5 V
100
200
---
ns
NA
t
FLTCLR
1.3
1.65
2
ms
V
IN
= 0 V or 5 V
V
ITRIP
= 0 V
t
ITRIP
500
750
1200
V
ITRIP
=5 V
---
400
190
---
400
575
300
---
---
950
420
60
V
IN
= 0 V or 5 V
V
ITRIP
= 5 V
V
IN
= 0 V & 5 V without
external deadtime
V
IN
= 0 V & 5 V with external
deadtime larger than DT
PW input=10 μs
MT
Delay matching time (t
ON
, t
OFF
)
---
---
50
PM
The minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the
input filter is exceeded.
This parameter applies to all of the channels. Please see the application section for more details.
PM is defined as PW
IN
- PW
OUT
.
Pulse width distortion
---
---
75
ns
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