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IRS2166D(S)PbF
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Page 13
0
0
I
LPFC
PFC
pin
near peak region of
rectified AC line
near zero-crossing region
of rectified AC line
Fig. 12:
On-time modulation near the zero-crossings
decrease below the internal 4.0 V threshold (V
BUSREG
), a
watch-dog pulse is forced on the PFC pin and normal
PFC operation is resumed.
Undervoltage Reset (UVR)
When the line input voltage is decreased, interrupted or a
brown-out condition occurs, the PFC feedback loop
causes the on-time of M
PFC
to increase in order to keep
the DC bus constant. Should the on-time increase too
far, the resulting peak currents in L
PFC
can exceed the
saturation current limit of L
PFC
. L
PFC
will then saturate and
very high peak currents and di/dt levels will occur. To
prevent this, the maximum on-time is limited by limiting
the maximum voltage on the COMP pin with an external
zener diode D
COMP
(Fig. 8). As the line input voltage
decreases, the COMP pin voltage and therefore the on-
time will eventually limit. The PFC can no longer supply
enough current to keep the DC bus fixed for the given
load power and the DC bus will begin to drop.
Decreasing the line input voltage further will cause the
VBUS pin to eventually decrease below the internal 3 V
threshold (V
BUSUV
) (Fig. 9). When this occurs, V
is
discharged internally below V
CCUV
-, the IRS2166D enters
UVLO mode and both the PFC and ballast sections are
disabled (see State Diagram). The start-up supply
resistor to V
CC
, together with the micro-power start-up
current of the IRS2166D, determines the line input turn-
on voltage. This should be set such that the ballast turns
on at a line voltage level above the undervoltage turn-off
level, V
CCUV+
. It is the correct selection of the value of the
supply resistor to V
and the zener diode on the COMP
pin that correctly program the on and off line input voltage
thresholds for the ballast. With these thresholds correctly
set, the ballast will turn off due to the 3.0 V undervoltage
threshold (V
BUSUV
) on the VBUS pin, and on again at a
higher liine input voltage (hysterisis) due to the supply
resistor to V
. This hysterisis will result in a proper reset
of the ballast without flickering of the lamp, bouncing of
the DC bus or re-ignition of the lamp when the DC bus is
too low.
Ballast Design Equations
Note: The results from the following design equations can
differ slightly from experimental measurements due to IC
tolerances, component tolerances, and oscillator over-
and under-shoot due to internal comparator response
time.
Step 1: Program Deadtime
The deadtime between the gate driver outputs HO and
LO is programmed with timing capacitor C
T
and an
internal deadtime resistor R
DT
. The deadtime is the
discharge time of capacitor C
T
from 3/5 V
CC
to 1/3 V
CC
and is given as:
1475
=
T
DT
C
t
[s] (1)
or
1475
DT
T
t
C
=
[F] (2)
Step 2: Program Run Frequency
The final run frequency is programmed with timing
resistor R
T
and timing capacitor C
T
. The charge time of
capacitor C
T
from 1/3 V
CC
to 3/5 V
CC
determines the on-
time of HO and LO gate driver outputs. The run frequency
is therefore given as:
1
T
R
C
or
1
RUN
T
f
C
)
1475
51
.
2
+
=
T
RUN
f
[Hz] (3)
2892
02
.
=
T
R
[
] (4)
Step 3: Program Preheat Frequency
The preheat frequency is programmed with timing
resistors R
and R
, and timing capacitor C
. The timing
resistors are connected in parallel internally for the
duration of the preheat time. The preheat frequency is
therefore given as: