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參數(shù)資料
| 型號(hào)： | IRS2166DPBF |
| 廠商： | International Rectifier |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | PFC + BALLAST CONTROL IC |
| 中文描述： | PFC的鎮(zhèn)流器控制IC |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 454K |
| 代理商： | IRS2166DPBF |
www.DataSheet4U.com
IRS2166D(S)PbF
www.irf.com
Page 10
4
3
5uA
5
2
CPH
C
T
RPH
R
T
11
12
COM
LO
M2
RCS
OSC.
16
HO
M1
15
VS
R
T
C
CPH
C
T
Half-
Bridge
Output
I
LOAD
V
BUS
(+)
V
BUS
(-)
Load
Return
Half-
Bridge
Driver
IRS2166D
S4
R
PH
Fig. 3:
Preheat circuitry
gate of a p-channel MOSFET (S4) (see Fig. 4) that
connects pin RPH with pin RT. As pin CPH exceeds 10.8
V (V
CPHEOP
), the gate-to-source voltage of MOSFET S4
begins to fall below the turn-on threshold of S4. As pin
CPH continues to ramp towards V
CC
, switch S4 turns off
slowly. This results in resistor R
PH
being disconnected
smoothly from resistor R
, which causes the operating
frequency to ramp smoothly from the preheat frequency,
through the ignition frequency, to the final run frequency.
The over-current threshold on pin CS will protect the
ballast against a non-strike or open-filament lamp fault
condition. The voltage on pin CS is defined by the lower
half-bridge MOSFET current flowing through the external
current sensing resistor R
CS
. The resistor R
CS
therefore
programs the maximum allowable peak ignition current
(and therefore peak ignition voltage) of the ballast output
stage. The peak ignition current must not exceed the
maximum allowable current ratings of the output stage
MOSFETs. Should this voltage exceed the internal
threshold of 1.20 V (V
CSTH+
), the internal fault counter
begins counting the number of of sequential over-current
faults (see timing diagram). If the number of over-current
faults exceeds 50 (n
EVENTS
), the IC will enter FAULT mode
and gate driver outputs HO, LO and PFC will be latched
low.
Run Mode (RUN)
Once the lamp has successfully ignited, the ballast enters
run mode. The run mode is defined as the state the IC is
in when the lamp arc is established and the lamp is being
driven to a given power level. The run mode oscillating
frequency is determined by the timing resistor R
T
and
timing capacitor C
T
(see Design Equations, page 15).
Should hard-switching occur at the half-bridge at any time
due to an open-filament or lamp removal, the voltage
across the current sensing resistor, R
CS
, will exceed the
internal threshold of 1.20 V (V
CSTH+
) and the fault counter
will begin counting (see timing diagram). Should the
number of consecutive over-current faults exceed 50
(n
EVENTS
), the IC will enter fault mode and gate driver
outputs HO, LO and PFC will be latched low.
Fig.4:
Ignition circuitry
DC Bus Undervoltage Reset
Should the DC bus decrease too low during a brown-out
line condition or over-load condition, the resonant output
stage to the lamp can shift near or below resonance. This
can produce hard-switching at the half-bridge which can
damage the half-bridge switches or, the DC bus can
decrease too far and the lamp can extinguish. To protect
against this, the VBUS pin includes a 3.0 V undervoltage
threshold (V
BUSUV
). Should the voltage at the VBUS pin
decrease below 3.0 V, V
CC
will be discharged below the
V
- threshold and all gate driver outputs will be latched
low.
For proper ballast design, the designer should design the
PFC section such that the DC bus does not drop until the
AC line input voltage falls below the rated input voltage of
the ballast (see PFC section). When correctly designed,
the voltage measured at the VBUS pin will decrease
below the internal 3.0 V threshold (VBUSUV) and the
ballast will turn off cleanly. The pull-up resistor to V
(R
SUPPLY
) will then turn the ballast on again when the AC
input line voltage increases to the minimum specified
value causing V
CC
to exceed V
CCUV
+.
R
SUPPLY
should be set to turn the ballast on at the
minimum specified ballast input voltage. The PFC should
then be designed such that the DC bus decreases at an
input line voltage that is lower than the minimum specified
ballast input voltage. This hysteresis will result in clean
turn-on and turn-off of the ballast.
SD/EOL and CS Fault Mode (FAULT)
Should the voltage at the SD/EOL pin exceed 3.0 V
(V
EOLTH+
) or decrease below 1.0 V (V
EOLTH-
) during run
mode, an end-of-life (EOL) fault condition has occurred
and the IC enters fault mode. LO, HO, and PFC gate
driver outputs are all latched off in the ‘low’ state. C
PH
is
discharged to COM for resetting the preheat time. To exit
fault mode, V
CC
can be decreased below V
CCUV
- (ballast
power off) or the SD pin can be increased above 5.0 V
(V
) (lamp removal). Either of these will force the IC
to enter UVLO mode (see State Diagram, page 7). Once
4
3
5uA
5
2
CPH
CT
RPH
RT
11
12
COM
LO
M2
R
CS
OSC
16
HO
M1
15
VS
C
CPH
C
T
Half-
Bridge
Output
I
LOAD
(+)
V
BUS
(-)
Load
Return
Half-
Bridge
Driver
IRS2166D
1.3V
S
1
S
4
Comp 4
10
13
VCC
CS
R1
C
CS
S
3
Fault
Logic
V
BUS
R
T
R
PH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IRS2166DSPBF | PFC + BALLAST CONTROL IC |
| IRS2166DSTRPBF | PFC + BALLAST CONTROL IC |
| IRS2168DPBF | ADVANCED PFC + BALLAST CONTROL IC |
| IRS2168DSPBF | ADVANCED PFC + BALLAST CONTROL IC |
| IRS2168DSTRPBF | ADVANCED PFC + BALLAST CONTROL IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IRS2166DPBF | 制造商:International Rectifier 功能描述:MOSFET Driver IC |
| IRS2166DSPBF | 功能描述:功率驅(qū)動(dòng)器IC PFC BALLAST CTRL IC 600V 15.6V VCC ESD RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| IRS2166DSPBF | 制造商:International Rectifier 功能描述:MOSFET Driver IC |
| IRS2166DSTRPBF | 功能描述:功率驅(qū)動(dòng)器IC PFC & Ballast Cntrl IC RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| IRS21681DSPBF | 制造商:International Rectifier 功能描述:ADVANCED PFC AND BALLAST CONTROL IC - Rail/Tube 制造商:International Rectifier 功能描述:IC LIGHT BALLAST CONTROL |
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