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參數(shù)資料
| 型號： | IRF7807V |
| 廠商： | International Rectifier |
| 英文描述： | N Channel Application Specific MOSFET |
| 中文描述： | ?頻道專用MOSFET的 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 159K |
| 代理商： | IRF7807V |
IRF7807V
www.irf.com
3
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
P
loss
= P
conduction
+ P
switching
+ P
drive
+ P
output
This can be expanded and approximated by;
(
)
P
loss
=
I
rms
2
×
R
ds(on)
+
I
×
Q
gd
(
i
g
×
V
in
×
f
+
I
×
Q
gs2
i
g
×
V
in
×
f
+
Q
g
×
V
g
×
f
Q
oss
)
+
2
×
V
in
×
f
This simplified loss equation includes the terms Q
and Q
oss
which are new to Power MOSFET data sheets.
Q
is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
gs1
and Q
gs2
, can be seen from
Fig 1.
Q
indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached (t1) and the time the drain
current rises to I
(t2) at which time the drain volt-
age begins to change. Minimizing Q
is a critical fac-
tor in reducing switching losses in Q1.
Q
is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure 2 shows how Q
is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s C
and C
when multiplied by
the power supply input buss voltage.
Figure 1: Typical MOSFET switching waveform
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss
=
P
conduction
+
P
drive
+
P
output
(
+
Q
g
×
V
g
×
f
(
Q
oss
2
*
P
loss
=
I
rms
2
×
R
ds(on)
)
+
×
V
in
×
f
+
Q
rr
×
V
in
×
f
(
)
*dissipated primarily in Q1.
Power MOSFET Selection for DC/DC
Converters
4
1
2
Drain Current
Gate Voltage
Drain Voltage
t3
t2
t1
V
GTH
Q
G
Q
G
Q
G
t0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IRF7807VD1 | 功能描述:MOSFET N-CH 30V 8.3A 8-SOIC RoHS:否 類別:分離式半導(dǎo)體產(chǎn)品 >> FET - 單 系列:FETKY™ 標準包裝:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金屬氧化物 FET 特點:邏輯電平門 漏極至源極電壓(Vdss):200V 電流 - 連續(xù)漏極(Id) @ 25° C:18A 開態(tài)Rds（最大）@ Id, Vgs @ 25° C:180 毫歐 @ 9A，10V Id 時的 Vgs(th)（最大）:4V @ 250µA 閘電荷(Qg) @ Vgs:72nC @ 10V 輸入電容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安裝類型:通孔 封裝/外殼:TO-220-3 整包 供應(yīng)商設(shè)備封裝:TO-220FP 包裝:管件 |
| IRF7807VD1PBF | 功能描述:MOSFET FETKY 30V VBRDSS 25mOhms 9.5nC RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導(dǎo)通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| IRF7807VD1TR | 功能描述:MOSFET N-CH 30V 8.3A 8-SOIC RoHS:否 類別:分離式半導(dǎo)體產(chǎn)品 >> FET - 單 系列:FETKY™ 標準包裝:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金屬氧化物 FET 特點:邏輯電平門 漏極至源極電壓(Vdss):200V 電流 - 連續(xù)漏極(Id) @ 25° C:18A 開態(tài)Rds（最大）@ Id, Vgs @ 25° C:180 毫歐 @ 9A，10V Id 時的 Vgs(th)（最大）:4V @ 250µA 閘電荷(Qg) @ Vgs:72nC @ 10V 輸入電容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安裝類型:通孔 封裝/外殼:TO-220-3 整包 供應(yīng)商設(shè)備封裝:TO-220FP 包裝:管件 |
| IRF7807VD1TRPBF | 功能描述:MOSFET MOSFT w/Schttky 30V 8.3A 25mOhm 9.5nC RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導(dǎo)通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
| IRF7807VD2 | 功能描述:MOSFET N-CH 30V 8.3A 8-SOIC RoHS:否 類別:分離式半導(dǎo)體產(chǎn)品 >> FET - 單 系列:FETKY™ 標準包裝:1,000 系列:MESH OVERLAY™ FET 型:MOSFET N 通道，金屬氧化物 FET 特點:邏輯電平門 漏極至源極電壓(Vdss):200V 電流 - 連續(xù)漏極(Id) @ 25° C:18A 開態(tài)Rds（最大）@ Id, Vgs @ 25° C:180 毫歐 @ 9A，10V Id 時的 Vgs(th)（最大）:4V @ 250µA 閘電荷(Qg) @ Vgs:72nC @ 10V 輸入電容 (Ciss) @ Vds:1560pF @ 25V 功率 - 最大:40W 安裝類型:通孔 封裝/外殼:TO-220-3 整包 供應(yīng)商設(shè)備封裝:TO-220FP 包裝:管件 |
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