www.irf.com
1
02/19/07
IRF6712SPbF
IRF6712STRPbF
DirectFET
Power MOSFET
Description
The IRF6712SPbF combines the latest HEXFET Power MOSFET Silicon technology with the advanced DirectFET
TM
packaging to achieve
the lowest on-state resistance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The DirectFET package is
compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection
soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET pack-
age allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6712SPbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies. The IRF6712SPbF has been optimized for parameters that are critical in synchronous buck
operating from 12 volt bus converters including Rds(on) and gate charge to minimize losses
.
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
SQ
SX
ST
Fig 1.
Typical On-Resistance Vs. Gate Voltage
Fig 2.
Typical Total Gate Charge vs Gate-to-Source Voltage
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
T
C
measured with thermocouple mounted to top (Drain) of part.
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
J
= 25°C, L = 0.14mH, R
G
= 25
, I
AS
= 13A.
DirectFET
ISOMETRIC
MQ
MX
MT
MP
RoHS Compliant Containing No Lead and Bromide
Low Profile (<0.7 mm)
Dual Sided Cooling Compatible
Ultra Low Package Inductance
Optimized for High Frequency Switching
Ideal for CPU Core DC-DC Converters
Optimized for both Sync.FET and some Control FET
application
Low Conduction and Switching Losses
Compatible with existing Surface Mount Techniques
100% Rg tested
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
VGS, Gate -to -Source Voltage (V)
0
2
4
6
8
10
12
T
)
ID = 17A
TJ = 25°C
TJ = 125°C
0
2
4
6
8
10
12
14
16
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VG
VDS= 20V
VDS= 13V
ID= 13A
Q
g tot
13nC
Q
gd
4.4nC
Q
gs2
1.7nC
Q
rr
14nC
Q
oss
V
gs(th)
10nC
1.9V
Absolute Maximum Ratings
Parameter
Units
V
V
DS
V
GS
I
D
@ T
A
= 25°C
I
D
@ T
A
= 70°C
I
D
@ T
C
= 25°C
I
DM
E
AS
I
AR
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Single Pulse Avalanche Energy
Avalanche Current
A
mJ
A
13
Max.
25
13
68
130
13
±20
17
V
DSS
25V max
V
GS
R
DS(on)
3.8m
@ 10V
R
DS(on)
6.7m
@ 4.5V
±20V max