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參數資料
| 型號： | IP82C55AZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Programmable Peripheral Interface |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, PDIP40 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-011AC, DIP-40 |
| 文件頁數： | 11/29頁 |
| 文件大?。?/td> | 563K |
| 代理商： | IP82C55AZ |
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11
FN2969.10
November 16, 2006
Operating Modes
Mode 2 (Strobed Bidirectional Bus I/O)
This functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O). “Hand shaking” signals are provided to
maintain proper bus flow discipline similar to Mode 1. Interrupt
generation and enable/disable functions are also available.
Mode 2 Basic Functional Definitions:
Used in Group A only
One 8-bit, bidirectional bus Port (Port A) and a 5-bit
control Port (Port C)
Both inputs and outputs are latched
The 5-bit control port (Port C) is used for control and
status for the 8-bit, bidirectional bus port (Port A)
Bidirectional Bus I/O Control Signal Definition
(Figures 11, 12, 13, 14)
INTR
- (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
Output Operations
OBF
- (Output Buffer Full). The OBF output will go “l(fā)ow” to
indicate that the CPU has written data out to port A.
ACK
- (Acknowledge). A “l(fā)ow” on this input enables the three-
state output buffer of port A to send out the data. Otherwise,
the output buffer will be in the high impedance state.
INTE 1
- (The INTE flip-flop associated with OBF).
Controlled by bit set/reset of PC4.
Input Operations
STB
- (Strobe Input). A “l(fā)ow” on this input loads data into the
input latch.
IBF
- (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
INTE 2
- (The INTE flip-flop associated with IBF). Controlled
by bit set/reset of PC4.
FIGURE 9. MODE 1 (STROBED OUTPUT)
tWOB
tWB
tAK
tAIT
tAOB
tWIT
OBF
WR
INTR
ACK
OUTPUT
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
FIGURE 10. COMBINATIONS OF MODE 1
1
D7
0
D6
1
D5
1
D4
1/0
D3 D2 D1 D0
CONTROL WORD
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
PC4
8
OBFB
PA7-PA0
STBA
INTRB
PC0
PC6, PC7
2
WR
PC6, PC7
1 = INPUT
0 = OUTPUT
8
IIBFA
PC5
INTRA
PC3
ACKB
PC2
I/O
PC1
PB7, PB0
RD
1
0
1
D7
0
D6
1
D5
0
D4
1/0
D3 D2 D1 D0
CONTROL WORD
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
PC7
8
STBB
PA7-PA0
OBFA
INTRB
PC0
PC4, PC5
2
RD
PC4, PC5
1 = INPUT
0 = OUTPUT
8
ACKA
PC6
INTRA
PC3
IBFB
PC1
I/O
PC2
PB7, PB0
WR
1
1
82C55A
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