參數(shù)資料
型號(hào)： IP82C55AZ
廠商： INTERSIL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： CMOS Programmable Peripheral Interface
中文描述： 24 I/O, PIA-GENERAL PURPOSE, PDIP40
封裝： ROHS COMPLIANT, PLASTIC, MS-011AC, DIP-40
文件頁(yè)數(shù)： 10/29頁(yè)
文件大小： 563K
代理商： IP82C55AZ
10
FN2969.10
November 16, 2006
INTR (Interrupt Request)
A “high” on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the condition: STB is a “one”, IBF is a “one” and INTE is a
“one”. It is reset by the falling edge of RD. This procedure
allows an input device to request service from the CPU by
simply strobing its data into the port.
INTE A
Controlled by bit set/reset of PC4.
INTE B
Controlled by bit set/reset of PC2.
Output Control Signal Definition
(Figure 8 and 9)
OBF
- (Output Buffer Full F/F). The OBF output will go “l(fā)ow”
to indicate that the CPU has written data out to the specified
port. This does not mean valid data is sent out of the port at
this time since OBF can go true before data is available.
Data is guaranteed valid at the rising edge of OBF, (See
Note 1). The OBF F/F will be set by the rising edge of the
WR input and reset by ACK input being low.
ACK
- (Acknowledge Input). A “l(fā)ow” on this input informs the
82C55A that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).
INTR
- (Interrupt Request). A “high” on this output can be
used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when
ACK is a “one”, OBF is a “one” and INTE is a “one”. It is reset
by the falling edge of WR.
INTE A
Controlled by Bit Set/Reset of PC6.
INTE B
Controlled by Bit Set/Reset of PC2.
NOTE:
1. To strobe data into the peripheral device, the user must operate
the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generates an ACK from the
peripheral device and then latch data into the peripheral device
on the rising edge of OBF.
FIGURE 7. MODE 1 (STROBED INPUT)
tST
STB
INTR
RD
INPUT FROM
PERIPHERAL
IBF
tSIB
tSIT
tPH
tPS
tRIT
tRIB
FIGURE 8. MODE 1 OUTPUT
1
D7
0
D6
1
D5
1
D4
1/0
D3 D2 D1 D0
CONTROL WORD
MODE 1 (PORT A)
PC7
8
ACKA
PC6
PA7-PA0
OBFA
INTRA
PC3
PC4, PC5
2
WR
PC4, PC5
1 = INPUT
0 = OUTPUT
1
D7 D6 D5 D4 D3 D2 D1 D0
CONTROL WORD
MODE 1 (PORT B)
PC1
8
ACKB
PC2
INTE
B
PB7-PB0
OBFB
INTRB
PC0
WR
1
0
INTE
A
82C55A
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