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參數(shù)資料
| 型號： | IMISG518CZ |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 70K |
| 代理商： | IMISG518CZ |
SG517/18
SYSTEM CLOCK GENERATOR
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev. 1.2
4/17/2000
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 408-263-6571
Page 3 of 6
IMI
SG517
and
SG518
8
7
6
5
1
2
3
4
OE
VDD
CLK-C
CLK-B
XTALOUT
XTALIN
GND
CLK-A
Figure 2. 8-Pin SOIC Package Pin Configuration
Pin Descriptions
Pin No.
Pin Name
I/O
TYPE
Description
1
CLK-A
O
TTL
CLK-A provides the required NTSC or PAL clock frequencies:
SG517 (NTSC) : 53.693175 MHz or SG518 (PAL) : 53.203425 MHz
2
GND
Ground
Power Ground
3 and 4
XTALIN
and
XTALOUT
I and O
CMOS
Pins form an on-chip reference oscillator when connected to terminals
of an external parallel resonant crystal. XTALIN may be connected to
a TTL/CMOS external clock source. AC coupling may be required. If
XTALIN is connected to an external clock other than a crystal, leave
XTALOUT (pin 4) unconnected.
5
CLK-B
O
TTL
CLK-B provides 67.7360005 and 67.7358420 MHz for SG517(NTSC)
and SG518(PAL) versions respectively
6
CLK-C
O
TTL
CLK-C provides the required NTSC or PAL clock frequencies:
SG517(NTSC): 3.579545 MHz or SG518(PAL) : 4.43361875 MHz.
These frequencies are derived by dividing the external input crystal
frequency by 4.
7
VDD
Power
Positive Power Supply, +3.3V +/-10%
8
OE
I
CMOS
Output Enable function control pin. The Clock-A, B and C are enabled
if the digital input is logic high (VDD) and disabled (High-Z) if this input
is low (GND).
Table 1
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