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參數(shù)資料
| 型號(hào)： | IMIZ9104DAB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 120K |
| 代理商： | IMIZ9104DAB |
Variable Delay Motherboard Clock Buffer
Z9104
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07083 Rev. *C
Revised May 6, 2002
Features
Output phase relationship is precisely controllable with
respect to input clock via a dedicated external feedback
path
Two-kV ESD protected
Six low-skew clocks generated
One 2.5V output clock
Outputs are individually enabled
Output frequencies from 30 to 120 MHz
3.3V power supply
Synchronous output enable and disable control
45–55% output duty cycle
±100 ps cycle-to-cycle jitter
32-lead TQFP package
Pin-compatible with MPC932P
Note:
1.
Multiplication Factor – The multiplication factor for these configurations is
the output frequency with respect to REFIN (FOUT = FIN × multiplication
factor).
Table 1. Feedback Scale Select Codes
Mode
FBS1
FBS0
Pcounter
Ncounter
MF[1]
00
0
4
82.0
00
1
4
10
2.5
01
0
4
12
3.0
01
1
8
12
1.5
10
0
4
41.0
10
1
4
5
1.25
11
0
4
61.5
11
1
8
81.0
Block Diagram
Pin Configuration
Z9104
VDDA
MOD
E
SC25
SC2,
3
VSS
CLK25
VDD25
CLK2
VSSA
SC6
SC5
SC4
FBI
N
VDDF
FBO
U
T
VSSF
VSS
CLK3
VDD
CLK4
VSS
CLK5
VDD
CLK6
VDDI
REFIN
PLLEN
FBS0
FBS1
OEALL
STOPCLK
VSSI
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
MODE
Ncounter
FBS0
FBS1
Stop
Logic
1
0
Stop
Logic
Stop
Logic
Stop
Logic
Stop
Logic
Pcounter
SC25
SC2,3
SC4
SC5
SC6
CLK6
CLK5
CLK4
CLK3
CLK25
PLL
REFIN
FBIN
FBOUT
PLLEN
VDDF
OEALL
CLK2
STOPCLK
VDD25
VDD
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