參數(shù)資料
型號： IF280C52EXXX-36:D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 51/143頁
文件大?。?/td> 4602K
15
XMEGA A3BU [DATASHEET]
8362F–AVR–02/2013
8.
DMAC – Direct Memory Access Controller
8.1
Features
Allows high speed data transfers with minimal CPU intervention
from data memory to data memory
from data memory to peripheral
from peripheral to data memory
from peripheral to peripheral
Four DMA channels with separate
transfer triggers
interrupt vectors
addressing modes
Programmable channel priority
From 1 byte to 16MB of data in a single transaction
Up to 64KB block transfers with repeat
1, 2, 4, or 8 byte burst transfers
Multiple addressing modes
Static
Incremental
Decremental
Optional reload of source and destination addresses at the end of each
Burst
Block
Transaction
Optional interrupt on end of transaction
Optional connection to CRC generator for CRC on DMA data
8.2
Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from
1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source
and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.
相關(guān)PDF資料
PDF描述
IT80C52CXXX-16:RD 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
IT80C52EXXX-36SHXXX:R 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44
IT80C52XXX-20:D 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44
IV80C52EXXX-25:RD 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44
IDT75T43100S66BS SPECIALTY MICROPROCESSOR CIRCUIT, PBGA304
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IF280C52-L16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
IF280C52T-12 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
IF280C52T-16 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
IF280C52T-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
IF280C52T-25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
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