- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄65593 > IDTCSP5992-5JRI (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 PDF資料下載
參數(shù)資料
| 型號： | IDTCSP5992-5JRI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 123K |
| 代理商： | IDTCSP5992-5JRI |
5
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSP5992
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
NOTES:
1. All timing tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with the specified load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only
in Divide-by-2 or Divide-by-4 mode).
6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
7. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
8. tPD is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
9. Measured at 0.8VDD.
10. Measured at 0.2VDD.
11. Refer to Input Timing Requirements table for more detail.
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
—
10
ns/V
tPWC
Input clock pulse, HIGH or LOW
3
—
ns
DH
Input duty cycle
10
90
%
REF
Reference Clock Input
10
85
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
CSP5992-2
CSP5992-5
CSP5992-7
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
FNOM
VCO Frequency Range
See PLL Programmable Skew Range and Resolution Table
tRPWH
REF Pulse Width HIGH (1)
3—
—
3
—
3
—
ns
tRPWL
REF Pulse Width LOW (1)
3—
—
3
—
3
—
ns
tU
Programmable Skew Time Unit
See Skew Selection Table for Output Pairs
tSKEWPR
Zero Output Matched-Pair Skew (xQ0, xQ1) (1,2, 3)
—
0.05
0.2
—
0.1
0.25
—
0.1
0.25
ns
tSKEW0
Zero Output Skew (All Outputs) CL = 0pF(1, 4)
—
0.1
0.25
—
0.25
0.5
—
0.3
0.75
ns
tSKEW1
Output Skew
(Rise-Rise, Fall-Fall, Same Class Outputs)(1, 3)
—
0.25
0.5
—
0.6
0.7
—
0.6
1
ns
tSKEW2
Output Skew
(Rise-Fall, Nominal-Inverted, Divided-Divided)(1, 5)
—
0.5
01.2
—
0.6
1.5
—
0.5
1.5
ns
tSKEW3
Output Skew
(Rise-Rise, Fall-Fall, Different Class Outputs)(1, 5)
—
0.25
0.5
—
0.5
0.7
—
0.7
1.2
ns
tSKEW4
Output Skew
(Rise-Fall, Nominal-Divided, Divided-Inverted)(1, 2)
—
0.5
0.9
—
0.6
1.7
—
1.2
1.7
ns
tDEV
Device-to-Device Skew( 1,2, 6)
—
0.75
—
1.25
—
1.65
ns
tPD
REF Input to FB Propagation Delay( 1,8)
0.25
00.25
0.5
00.5
0.7
00.7
ns
tODCV
Output Duty Cycle Variation from 50% (1)
1.2
01.2
1.2
01.2
1.5
01.5
ns
tPWH
Output HIGH Time Deviation from 50% (1,9)
——
3
—
4
—
5.5
ns
tPWL
Output LOW Time Deviation from 50% (1,10)
——
3
—
4
—
5.5
ns
tORISE
Output Rise Time(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tOFALL
Output Fall Time(1)
0.5
2
2.5
0.5
2
3.5
0.5
3
5
ns
tLOCK
PLL Lock Time(7)
—
0.5
—
0.5
—
0.5
ms
tJR
Cycle-to-Cycle Output Jitter
RMS
—
25
—
25
—
25
ps
Peak-to-Peak
—
200
—
200
—
200
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDTCSP5V991-5JR | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| IDTCSP5V991-2JR | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| IDTCSP5V993-5QI | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| IDTCSP5V993-5Q | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| IDTCSPT855PA | PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPF2510C | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPGG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPGGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
| IDTCSPF2510CPGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V PHASE-LOCK LOOP CLOCK DRIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復。