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參數(shù)資料
| 型號： | IDTCSP5V991-2JR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 122K |
| 代理商： | IDTCSP5V991-2JR |
1
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSP5V991
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
G ND/sO E
1Q0
Skew
Select
1Q1
1F1:0
3
2Q0
Skew
Select
2Q1
2F1:0
FS
3
REF
PLL
FB
3
3Q0
Skew
Select
3Q1
3F1:0
3
4Q0
4Q1
Skew
Select
4F1:0
3
VCCQ /PE
FEBRURARY 2000
2000
Integrated Device Technology, Inc.
DSC-5786/-
c
IDTCSP5V991
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK
FEATURES/BENEFITS
REF is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 6.25Hz to 85MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
CSP5V991-2: t
SKEW0<250ps
CSPV991-5: t
SKEW0<500ps
CSPV991-7: t
SKEW0<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps peak-to-peak
Industrial temperature range
Available in 32-pin PLCC Package
DESCRIPTION
The CSP5V991 is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The CSP5V991 has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the GND/
sOE pin is held low, all the outputs are synchronously
enabled. However, if GND/
sOE is held high, all the outputs except 3Q0 and
3Q1 are synchronously disabled.
Furthermore, when the VCCQ/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input. When VCCQ/
PE is held low, all the outputs are synchronized with the negative edge of
REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
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