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參數(shù)資料
| 型號(hào)： | IDTCSP5992-2JR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 123K |
| 代理商： | IDTCSP5992-2JR |
7
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDTCSP5992
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
RE F
FB
Q
OTHER Q
INVER TED Q
REF D IVIDE D B Y 2
REF D IVIDE D B Y 4
t REF
t PD
tSKEWPR
t SKEW0, 1
t SKEW 2
t SKEW3, 4
tSKEW1, 3, 4
t SKEW2, 4
t SKEW3, 4
t SKEW 2
t SKEWPR
t SKEW0, 1
tJR
tODCV
t ODCV
t RPWH
tRPW L
AC TIMING DIAGRAM
NOTES:
VDDQ/PE: The AC Timing Diagram applies to VDDQ/PE=VDD. For VDDQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided
outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 50pF (30pF for -2 and -5) and terminated with 50
to VDD/2.
tSKEWPR:
The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0:
The skew between outputs when they are selected for 0tU
.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.)
tODCV:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tPWH is measured at 0.8VDD.
tPWL is measured at 0.2VDD.
tORISE and tOFALL are measured between 0.2 VDD and 0.8VDD.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
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