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參數(shù)資料
| 型號(hào)： | IDT89HPES8T5ZHBCG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/31頁 |
| 文件大小： | 0K |
| 描述： | IC PCI SW 8LANE 5PORT 324-BGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | PRECISE™ |
| 類型： | PCI Express 開關(guān) - Gen1 |
| 應(yīng)用： | 服務(wù)器，儲(chǔ)存，通信，嵌入式，消費(fèi)品 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-LBGA |
| 供應(yīng)商設(shè)備封裝： | 324-CABGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 89HPES8T5ZHBCG |
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March 27, 2008
IDT 89HPES8T5 Data Sheet
Figure 6 GPIO AC Timing Waveform
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal
Symbol Reference
Edge
Min Max Unit
Timing
Diagram
Reference
GPIO
GPIO[10:0]1
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
Tpw_13b2
2. The values for this symbol were determined by calculation, not by testing.
None
50
—
ns
See Figure 6.
Table 11 GPIO AC Timing Characteristics
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK
Tper_16a
none
50.0
—
ns
See Figure 7.
Thigh_16a,
Tlow_16a
10.0
25.0
ns
JTAG_TMS1,
JTAG_TDI
1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b
JTAG_TCK rising
2.4
—
ns
Thld_16b
1.0
—
ns
JTAG_TDO
Tdo_16c
JTAG_TCK falling
—
20
ns
Tdz_16c2
2. The values for this symbol were determined by calculation, not by testing.
—20
ns
JTAG_TRST_N
Tpw_16d2
none
25.0
—
ns
Table 12 JTAG AC Timing Characteristics
Tdo_13a
Tpw_13b
EXTCLK
GPIO (synchronous output)
GPIO (asynchronous input)
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