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參數(shù)資料
| 型號： | IDT89HPES8T5ZHBCG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 26/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI SW 8LANE 5PORT 324-BGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | PRECISE™ |
| 類型： | PCI Express 開關(guān) - Gen1 |
| 應(yīng)用： | 服務(wù)器，儲存，通信，嵌入式，消費(fèi)品 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-LBGA |
| 供應(yīng)商設(shè)備封裝： | 324-CABGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 89HPES8T5ZHBCG |
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March 27, 2008
IDT 89HPES8T5 Data Sheet
Figure 4 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES8T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES8T5 utilizes
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-
ever the state of a Hot-Plug output needs to be modified, the PES8T5 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES8T5. In response to an I/O expander interrupt, the PES8T5 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES8T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate
functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES8T5. Some of the functions listed may be multiplexed onto the same pin. The
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note: In the PES8T5, the 4 downstream ports are labeled ports 2 through 5. There is no port 1.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
PE2RP[0]
PE2RN[0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[0]
PE2TN[0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE3RP[0]
PE3RN[0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PE3TP[0]
PE3TN[0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
Table 2 PCI Express Interface Pins (Part 1 of 2)
Processor
PES8T5
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES8T5
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
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